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Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits |
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Testing of digital-to-analog converters |
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Method and apparatus for failure detection utilizing functional test vectors and scan mode |
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Testing apparatus embedded in scribe line and a method thereof |
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Method and apparatus for light-controlled circuit characterization |
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Method and system for instrumenting simulation models |
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Process for transmitting information bits with error correction coding and decoder for the implementation of this process
| Details |
Inventors: Pyndiah, Ramesh; Adde, Patrick;
Assignee: France Telecom (Paris, FR)
Primary Examiner: Grant; William
Assistant Examiner: Marc; McDieunel
Attorney, Agent or Firm: Marshall, O'Toole, Gerstein, Murray & Borun
The bits transmitted are coded according to the product of at least two systematic block codes. Iterative decoding is applied in order to determine, at each code word search step, a data matrix ({R}) and a decision matrix ({D}) used for the following step. The new decision matrix is determined at each step by decoding the lines or columns of the input matrix, and the new data matrix is determined taking into account the correction terms which increase the reliability of the decoding on each iteration. The coding and decoding circuits (17) are rendered programmable by a shortening technique allowing selection of the number k-X of non-redundant information bits per block to be coded. Known values are assigned to the other bits, the positions of which are uniformly distributed according to each dimension of the matrices. |
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DETAILED DESCRIPTION The invention therefore proposes in a process of the type indicated in the introduction, that the first binary matrix comprises, in addition to the information bits, a set of bits with values a priori known to the receiver, which are distributed in an approximately uniform manner according to each dimension of the first binary matrix, which, after systematic coding, are located in determined positions of the said second binary matrix, and which are not transmitted towards the channel, and that the receiver places in the input matrix, in positions corresponding to the said determined positions of the second binary matrix, samples the signs of which correspond respectively to the a priori known values of the bits of the said set and the absolute values of which are representative of a maximum confidence. The invention makes use of a technique similar to shortening techniques which are well known in the field of simple block codes. Let n, k and d be the product code parameters, in the form: ##EQU1## where L is the number of elementary codes the respective parameters of which are (n. sub. i, k. sub. i, d. sub. i) (the case where L=2 is considered below, without limiting generality). k and n are the respective numbers of bits in the "first" and "second" binary matrices. The invention allows the number of independent information bits contained in the matrix to be adapted to any number k-X less than or equal to k, the receiver decoding circuit being the same whatever the number X of a priori known bits. The positions of these X bits are uniformly distrubted in the first matrix, which allows optimum usage of the performance of the iterative decoding process. On this point, it should be noted that a shortening of one or more codes into elementary blocks would be less advantageous as it would allow less choice in the value of X, and especially as it would lead to certain elementary decodings resulting in no BER gain. The parameters (n',k',d') of the shortened product code are finally n'=n-X, k'=k-X and d'=d
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