DETAILED DESCRIPTION What is claimed is: 1.
A variable length, high speed, digital delay line apparatus comprising in combination: a set of serially arranged, fixed-length, digital delay units, and a set of switching units interposed respectively between each of said set of delay units, said set of switching units having a set of switching position, said set of switching positions being one greater than the rank of the switching unit position within the delay unit chain, each switching position of said set of switching units being connected to a switching position within a switching unit of greater rank, each of said set of switching units being respectively selectable.
2.
A variable length, high speed, digital delay line apparatus as described in claim 1 further including digital decoding means for selecting one of said set of switching units, said digital decoding means being interconnected with each of said set of switching units.
3.
A variable length, high speed, digital delay line apparatus as described in claim 1 wherein said set of digital delay units comprise in combination: a set of shift registers having a geometrically increasing varying number of binary stages.
4.
A variable length, high speed, digital delay line apparatus as described in claim 1 wherein said set of switching units comprise in combination: a set of binary selector units, each respectively having a progressively increasing number of digital selector bits therein, said selector positions varying between 2 and N-1, where N is any positive integer greater than 0.
5.
A variable length, high speed, digital delay line apparatus as described in claim 2 wherein said digital selecting means comprises in combination: a binary decoding circuit to receive an N-bit delay length word, said binary decoding circuit decoding said N-bit delay length word to activate the proper switching units of said set of switching units to provide the desired delay time.
6.
A variable length, high speed, digital delay line apparatus as described in claim 3 wherein said number of binary stages varies between one and 2N
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Fault Detection 
