Protocol for interrupt bus arbitration in a multi-processor system

DETAILED DESCRIPTION One object of the present invention is to provide for a multi-processor programmable interrupt controller (MPIC) system that uses an integrated circuit chip incorporating both the local processor and an mimed local processor interrupt controller as a single unit.
Another object is to provide a multi-processor programmable interrupt controller (MPIC) system including but not limited to the following capabilities: 1) multiple I/O peripheral devices, each with its own set of interrupts; 2)static as well as dynamic multi-processor interrupt management including the symmetrical distribution of interrupts over selected processors; 3) level or edge triggered interrupt request pins, software selectable per pin; 4) per pin programmable interrupt vector and steering information; 5) programmable vector address field defined by each operating system; 6) inter-processor interrupts allowing any processor to interrupt any other for dynamic reallocation of interrupt tasks; and 7) support of system wide support functions related to non-maskable interrupts (NMI), processor reset, and system debugging.
The present invention achieves these capabilities by means of an MPIC system structure which includes three major subsystems: 1) an I/O MPIC unit for acquiring interrupt request (IRQ) signals from its associated I/O peripheral devices, having a redirection table for processor selection and vector/priority information; 2) local-MPIC units which may be separate auxiliary units connected to the associated processor or units that am partially or totally integrated into the associated processor, each managing interrupt requests for a specific system processor including pending, nesting and masking operations, as well as inter-processor interrupt generation; and 3) a dedicated I/O bus, distinct from any system or memory bus, for communications between the I/O and local MPIC units as well as between local-MPIC units.
It is a further object of this invention to support system scaling granularity of one, i