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| Method and apparatus for inhibiting a predecoder when selecting a redundant row line |
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| Random access memory having a flexible array redundancy scheme |
| The present invention is a wide I/O Random Access Memory (RAM) and the architecture and redundancy ... |
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| Integrated circuit chip with a wide I/O memory array and redundant data lines |
| The present invention is an integrated circuit chip with a RAM or a RAM macro with at least one ... |
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| Improved logic cell array using CMOS E.sup.2 PROM cells |
| OF ILLUSTRATIVE EMBODIMENT Referring now to the drawings, FIG. 1 is a schematic block diagram of a ... |
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| DRAM architecture having distributed address decoding and timing control |
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| Memory with page mode |
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RAM memory circuit having a plurality of banks and an auxiliary device for testing
| Details |
Inventors: Boldt, Sven; Pfeiffer, Johann;
Assignee: Infineon Technologies AG (Munich, DE)
Primary Examiner: Le; Vu A.
Assistant Examiner:
Attorney, Agent or Firm: Patterson & Sheridan, L.L.P.
One embodiment of the invention provides a RAM memory circuit having k≧2 banks, each of which having a multiplicity of memory cells and a selection device to simultaneously select groups of in each case n≧2 memory cells of the bank for the writing or reading of n parallel data. For the fast testing of all the banks, devices are included for the parallel switching of the banks such that reading and writing may be effected simultaneously at all the banks. For each bank, a dedicated evaluation device is included for comparing the n data respectively read out at the relevant bank with a reference information item, which is representative of the write data which have previously been written in at the currently selected memory cell group of the bank, and for providing a result information item, comprising 1≦m≦n/k bits, each of which indicates whether a subset precisely assigned to it from m subsets of the n read data corresponds to a part of the reference information item which is precisely assigned to said subset. |
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DETAILED DESCRIPTION One aspect of the invention is directed to designing a RAM memory circuit provided with a plurality of memory banks such that the circuit may be tested in a shorter time than hitherto.
Accordingly, one embodiment of the invention provides a RAM memory circuit containing: k≧2 banks, each bank having a multiplicity of memory cells and a selection device to simultaneously select groups of n≧2 memory cells of the respective bank depending on a cell address information item applied and, at the respectively selected memory cell group, to write in a group of n data, via an assigned n-bit bank bus, as write data in a write operation or to read out said group as read data in a read operation; a bidirectional data port with n transfer channels which are designed for receiving and transmitting n parallel data and can be connected to selectable specimens of the bank buses; a test auxiliary device, which has a bus parallel switching device for simultaneously connecting all k bank buses to the data port and a selection parallel switching device for simultaneously activating the selection devices of all the banks.
The test auxiliary device contains a test control circuit, which responds to a test mode setting signal to activate the bus parallel switching device only during the write operation, to decouple all the bank buses from the data port during the read operation, and to activate the selection parallel switching device during the write operation and during the read operation.
Furthermore, the test auxiliary device contains for each bank a dedicated evaluation device for comparing the n read data that appear on the assigned bank bus with a reference information item, which is representative of the write data which have previously been written in at the currently selected memory cell group, and for providing a result information item, comprising 1≦m≦n/k bits, each of which indicates whether a subset precisely assigned to the respective bit from m subsets of the n read data corresponds to a part of the reference information item which is precisely assigned to the respective subset
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Fault Detection 
