Random access memory having a flexible array redundancy scheme

DETAILED DESCRIPTION The present invention is a wide I/O Random Access Memory (RAM) and the architecture and redundancy scheme, therefor.
If the RAM is large, it is divided into units.
For each unit, or for smaller RAMs, the memory is further sub-divided into blocks.
The blocks are subdivided into segments.
The segments are arranged in rows and columns and each segment includes at least one spare column.
Optionally, the segments may also include spare rows.
Row selection is responsive to a row address and is common for all segments in a block.
During any array access, only half of the segments in a block are accessed.
The redundant columns may be selected from the segments in the unaccessed half to replace a defective column in one or more accessed segments.
Selected redundant columns are swapped for defective columns late in the cycle, eliminating the need for a redundancy decode delay in the access.