Redundancy analyzer for automatic memory tester

DETAILED DESCRIPTION What is claimed is: 1.
Memory test apparatus for testing a memory under test (MUT) formed from physical structures which define a plurality of storage locations organized into a plurality of regions, said apparatus comprising: a) means for testing the plurality of storage locations in the MUT and generating fault signals indicating which of the plurality of storage locations in the MUT is faulty, b) a plurality of region modules, each said module having an input, and each said region module comprising: i) a region fault RAM storing data, ii) analysis means, connected to said region fault RAM, for analyzing the data in the region fault RAM to identify faulty structures within the MUT, and iii) input means, coupled to the input of the region module and the region fault RAM, for storing information from the input to the region fault RAM, and c) interface means, having an input connected to the means for testing and a plurality of outputs, each output coupled to a region module, for routing fault signals indicating a faulty location to the input of a region module which is selected based on the region of the MUT which contains the faulty location.
2.
The memory test apparatus of claim 1 wherein said interface means includes OR gates to combine fault signals indicating faulty storage locations in more than one region in the MUT.
3.
The memory test apparatus of claim 1 wherein said interface means includes multiplexers.
4.
The memory test apparatus of claim 1 wherein said interface means includes a transfer clock and the transfer clock is connected to all said region modules.
5.
The memory test apparatus of claim 1 wherein the means for testing comprises a catch RAM having data output nodes coupled to the fault signals.
6.
The memory test apparatus of claim 1 wherein said means for testing comprises a comparator having an output coupled to the fault signals.
7.
The memory test apparatus of claim 1 wherein said input means is a logic array.
8.
The memory test apparatus of claim 1 wherein the analysis means in each said region module includes a microprocessor and program RAM connected to the microprocessor