Redundancy circuitry layout for a semiconductor memory device

DETAILED DESCRIPTION In view of the state of the art described, the objective of the present invention is to provide a redundancy circuitry layout which minimizes the chip size overhead due to the implementation of redundancy.
According to the present invention, such objective is attained by means of a redundancy circuitry layout for a semiconductor memory, device, the redundancy circuitry comprising a first plurality of programmable non-volatile memory registers for the selection of redundancy bit lines of redundancy memory elements, and a second plurality of programmable non-volatile memory registers for the selection or redundancy word lines of redundancy memory elements.
One preferred embodiment of the present invention comprises an array of programmable non-volatile memory elements for storing the addresses of defective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines, and in that it is divided into identical layout strips which are perpendicular to said array of memory elements and which each comprise first and second strip sides located at opposite sides of the array of memory elements, the first strip side containing at least one memory register of the first plurality, and being crossed by a column address signal bus running parallel to the array of memory elements, the second strip side containing one memory register of the second plurality and being crossed by a row address signal bus running parallel to the array of memory elements.
Thanks to the present invention, and particularly to the fact that circuit blocks interacting both with each other and with the same signals have been physically grouped in a same chip region, the redundancy circuitry is very compact, and the increase in the overall chip size is therefore limited.