Redundant address decoder

DETAILED DESCRIPTION Accordingly, an object of the present invention is to provide a redundant address decoder which can improve the memory access speed by providing a sufficient increase in potential for a redundant word line when the redundant word line is selected.
In accordance with the present invention, there is provided a redundant address decoder comprising: a first circuit for outputting a match signal with active state when an input address AD matches a stored redundant address RA and for outputting a redundancy selection signal in response to a first part AD1 of the input address AD; an FET having a source connected to a redundant word line, a drain and a gate; a second circuit for supplying to the drain of the FET a high potential in case of the match signal being active and the redundancy selection signal being active and a low potential in case of others; and a third circuit for supplying to the gate of the FET a high potential in case of the redundancy selection signal being active and a low potential in case of the redundancy selection signal being inactive.
The FET may be an enhanced type MIS FET such as nMOS FET or an enhanced type MES FET such as GaAs FET.
With the present invention, since the third circuit can start operating sooner than in the prior art by the signal propagation delay time in the comparator portion when the potential of the drain of the FET rises, the potential of the gate of the FET will have already risen sufficiently high.
As a result, the increase in potential of the redundant word line is sufficient, improving the memory access speed.
In the first mode of the present invention, the first circuit comprises: a redundant address memory circuit for outputting a value D2 and a redundancy selection signal in response to the first part AD1 of the address AD, the value D2 being equal to a first part RA1 of the redundant address RA in case of the first part AD1 of the address AD being equal to a second part RA2 of the redundant address RA; and a comparator circuit for comparing the second part AD2 of the address AD and the value D2 from the redundant address memory circuit and for outputting the match signal with active state when the AD2 and the D2 match each other