Redundant clock system utilizing nonsynchronous oscillators

DETAILED DESCRIPTION In accordance with the present invention, there is provided a clock system with two nonsynchronized digital clocks, each having a select circuit for selecting the output signal of one of the clocks to be the present output of the system.
Each clock has logic capable of detecting errors in the operation of the other clock.
Each clock additionally has a switchover control for selecting the other output signal to be the system output when an error is detected in the presently selected clock.
The switchover control includes means for ensuring that the interval between pulses in the system output remains greater than a predetermined period.
The two clocks of the system of the invention can be embodied as two separate identical circuit cards.
The isolation of the two clocks thus achieved improves the possibility that one can continue proper operation when the other experiences a malfunction.
One of the advantages of the present invention is economic.
The present clock system avoids the use of circuitry necessary to achieve synchronization of its two clocks.
In a preferred embodiment, the process of switchover from a malfunctioning clock to the other clock includes the step of freezing the output of the malfunctioning clock in its present logical state.
This avoids the possibility of continuing to send a mixture of good and bad clock pulses to a utilizing circuit such as a processor.
The switchover sequence also preferably includes resetting the output of the frozen clock to a known state and then waiting at least one clock cycle before selecting the good clock output to become the system output.
The wait period prevents any occurrence of system output pulses separated by an interval shorter than the proper clock interval.
Clock pulses occurring too frequently could produce an indeterminate state in the logic of a circuit utilizing the clock system output.
It is a feature of the clock system of the invention that a malfunctioning clock does not try to stop itself nor to alter the state of the other clock