Refresh operation control circuit for semiconductor device

DETAILED DESCRIPTION An object of this invention is to provide a simple practical circuit to manage and control the timing of refresh such that the refresh operation is automatically carried out in the idle time of normal memory operation.
A further object of this invention is to provide a refresh operation timing control circuit of a semiconductor memory device that can effect management and control by a simple circuit construction such that the refresh operation is carried out with the appropriate timing.
This invention constitutes a refresh operation timing control circuit for a semiconductor memory device that automatically manages and controls the refresh operation in the idle time of normal memory operation.
Two flip-flop circuits temporarily hold a normal read start command signal and a refresh start command signal, respectively, generated within the memory device.
A normal operation/refresh operation priority determining circuit wherein two 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit.
The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the inputs.
Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.
This invention provides a refresh operation control circuit for controlling the normal read operation and the refresh operation of a semiconductor device, the device generating a normal start signal for starting the normal read operation and a refresh start signal for starting the refresh operation, comprising: first circuit means for latching the normal start signal; second circuit means for latching the refresh start signal; and priority determining circuit means generating first and second output signals and responsive to the first and second circuit means for determining priority between the first and second output signals, the first output signal for controlling the normal read operation and the second output signal for controlling the refresh operation of the device