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Preamplification method and apparatus for dram sense amplifiers
An object of the present invention is to improve reliability of read out in DRAM. Another object of the present invention is to increase the potential difference applied ...
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Semiconductor memory device
It is an object of the present invention to provide a semiconductor memory device including a FAMOS transistor type redundancy decoder circuit suitable for practical use....
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Semiconductor device
It is accordingly the object of this invention to provide a reliable semiconductor device which enables binary data to be stored in a nonvolatile memory element without ...
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Data stream smoothing using a FIFO memory
The present invention is directed to the use of a FIFO memory for communicating data from a DRAM to a testing device in a continuous data stream despite interruptions ...
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Semiconductor memory device having redundant circuit
Accordingly, a first object of this invention is to provide a semiconductor memory device capable of enhancing the access speed. A second object of this invention is to ...
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Redundant address decoder
Accordingly, an object of the present invention is to provide a redundant address decoder which can improve the memory access speed by providing a sufficient increase in ...
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Automatic transition charge pump for nonvolatile memories
Generally, the present invention provides a high voltage charge pump for programming a non-voltage memory that can operate at more than one power supply voltage. A low ...
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High speed static BiCMOS memory with dual read ports
A memory includes a plurality of cells with each cell containing a pair of cross-coupled N-channel field-effect transistors having set and reset nodes. Also in each cell,...
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Flexible redundancy architecture and fuse download scheme
What is claimed is: 1. In an integrated circuit comprising a plurality of circuit elements, some of which may be faulty, which respond to a discrete set of access ...
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Flexibilitiy for column redundancy in a divided array architecture
The present invention relates to an apparatus and method for implementing flexible redundancy memory blocks in a divided array architecture scheme incorporating a ...
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