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Replacement data error detector
| Details |
Inventors: Supnet, Erik P.;
Assignee: Broadcom Corporation (Irvine, CA)
Primary Examiner: Yoo; Do Hyun
Assistant Examiner: Dinh; Ngoc
Attorney, Agent or Firm: Merkel; Lawrence J. Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
A cache includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to eliminate the error. For example, a predetermined, fixed value may be used for the update of the replacement data. Each of the cache entries corresponding to the replacement data may be represented in the fixed value. In one embodiment, the error circuit may detect errors in the replacement data using only the replacement data (e.g. no parity or ECC information may be used). In this manner, errors may be detected even in the presence of multiple bit errors which may not be detectable using parity/ECC checking. |
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DETAILED DESCRIPTION A cache is described which includes an error circuit for detecting errors in the replacement data.
If an error is detected, the cache may update the replacement data to eliminate the error.
For example, a predetermined, fixed value may be used for the update of the replacement data.
Each of the cache entries corresponding to the replacement data may be represented in the fixed value.
By eliminating the error in the replacement data, the performance impacts of the error may be reduced.
In one embodiment, the error circuit may detect errors in the replacement data using only the replacement data (e.
g.
no parity or ECC information may be used).
In this manner, errors may be detected even in the presence of multiple bit errors which may not be detectable using parity/ECC checking.
Furthermore, inefficiency which may result if parity/ECC were used for the replacement data may be avoided, as may grouping the replacement data with other data for covering with parity/ECC data.
Broadly speaking, a cache is contemplated comprising a memory configured to store replacement data corresponding to a plurality of cache entries and a circuit coupled to receive the replacement data from the memory.
The circuit is configured to determine whether or not at least one of the plurality of cache entries is not represented in the replacement data.
Additionally, a method is contemplated.
Replacement data corresponding to a plurality of cache entries is received.
Whether or not at least one of the plurality of cache entries is not represented in the replacement data is determined.
Furthermore, a cache is contemplated, comprising a memory configured to store replacement data corresponding to a plurality of cache entries and a circuit coupled to receive the replacement data from the memory.
The replacement data indicates an order of the plurality of cache entries for replacement.
The circuit is configured to detect an error in the order if a different one of the plurality of cache entries is not indicated at each position in the order
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Fault Detection 
