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Row redundancy block architecture
| Details |
Inventors: DeBrosse, John; Kirihata, Toshiaki; Wong, Hing;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Nelms; David C.
Assistant Examiner: Mai; Son
Attorney, Agent or Firm: Whitham, Curtis, Whitham & McGinn, Schnurmann; H. Daniel
Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regardless of mode, eliminating the existing reliability concern. This two-input OR gate combined with row redundancy match detection works as an ideal sample wordline enable generator. |
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DETAILED DESCRIPTION It is therefore an object of the present invention to provide a redundancy block architecture which uses a row redundancy control circuit arrangement that effectively reduces design space.
It is a further object of the invention to provide a fast and reliable redundancy match detection by means of a NOR type redundancy match detection with an interchanged self-timing generator.
It is another object of the invention to provide a sample wordline enable (SWLE) generator which allows SWLE to set the sample wordline (SWL) at a time when wordline enable (WLE) sets the wordline (WL) regardless of normal or redundancy mode, while tracking the delay for the redundancy match detection.
The present invention is related to the invention disclosed in U.
S.
Pat.
No.
5,517,442 to Kirihata et al.
, the subject matter of which is incorporated herein by reference.
According to the present invention, row redundancy control circuits are arranged parallel to word direction and are arranged at the bottom of the redundancy block.
This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space.
According to another aspect of the invention, an illegal normal/redundancy access problem caused by the address versus timing skew has been solved.
The timing necessary for this detection is given locally by using its adjacent redundancy match detection.
This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection.
In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection.
One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL)
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Fault Detection 
