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Selectively updateable mapped data storage system
| Details |
Inventors: Mou, Yanan;
Assignee: United Microelectronics Corp. (Hsinchu, TW)
Primary Examiner: Cabeca; John W.
Assistant Examiner: Tran; Denise
Attorney, Agent or Firm: Thomas, Kayden, Horstemeyer & Risley
A selectively updateable mapped data storage system is provided. The data storage system includes an address decoder two improved CAM blocks, and a converter connected between the two improved CAM blocks. This selectively updateable mapped data storage system can be implemented with a smaller layout space on the chip and consumes less electrical power than the prior art. Moreover, this selectively updateable mapped data storage system allows the selective updating procedure to be easily and more efficiently implemented than through software means. The selectively updateable mapped data storage system is therefore more advantageous and cost-effective to use than the prior art. |
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DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS FIG.
6 is a schematic block diagram of the selectively updateable mapped data storage system according to the invention.
As shown, the data storage system of the invention includes an address decoder 68; a first improved CAM block 70 coupled to the address decoder 68 via a plurality of word lines 76 (AWL0-AWL255); and a second improved CAM block 72 coupled to the first improved CAM block 70 via a converter 74.
The first improved CAM block 70 is composed of a driver circuit 78, an array of CAM cells 80, and an I/O sense amplifier 82.
In CAM block 70, the driver circuit 78 receives a first set of memory data M DATA A(9:0) and stores it in the CAM cells 80, and the I/O sense amplifier 82 is used for the input/output of a first set of data DATA A(9:0).
Similarly, the second improved CAM block 72 is composed of a driver circuit 84, an array of CAM cells 86, and an I/O sense amplifier 88.
In CAM block 72, the driver circuit 84 receives a second set of memory data M DATA B(8:0) and stores it in the CAM cells 86, and the I/O sense amplifier 88 is used for the input/output of a second set of data DATA B(8:0).
In operation, the address decoder 68 receives an address signal ADD(7:0).
The decoded address data are then transferred through the word lines 76 (AWL0-AWL255) to the first improved CAM block 70, causing the first improved CAM block 70 to store the data from DATA A(9:0) into the corresponding CAM cells 80 in the first improved CAM block 70.
After the CAM cells 80 in the first improved CAM block 70 have received the first set of memory data M DATA A(9:0), it outputs a match drive signal through the a.
sub.
-- match bus to the converter 74, causing the converter 74 to enable the word lines WLb(255:0) to gain access to DATA B(8:0) stored in the corresponding CAM cells 86 in the second improved CAM block 72.
After the CAM cells 86 in the second improved CAM block 72 have received the memory data M DATA B(8:0), it outputs a match drive signal through the b
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Fault Detection 
