Self-isolating cross-coupled sense amplifier latch circuit

DETAILED DESCRIPTION It is accordingly an object of the present invention to provide an improved sense amplifier latching circuit using field effect transistors of both the enhancement and depletion mode.
It is another object of this invention to increase the speed of an electronic memory; It is still another object of this invention to reduce power requirements in the operation of an electronic memory; Lastly, it is an object of this invention to provide a sense amplifier latch designed for an integrated memory array in which there is no need to match the threshold voltage characteristics of the transistors in the sense amplifier latch.
In accordance with the present invention, a self-isolated, cross-coupled sense amplifier latching circuit comprising field effect transistors of both the enhancement and depletion mode is provided.
Briefly, first and second cross-coupled field effect transistors have their source electrodes connected in common and to a third field effect transistor which establishes a race condition after a small potential difference has been applied to the cross-coupled electrodes.
The small potential difference is applied through a pair of unidirectionally conducting devices which are connected between the input points and the cross-coupled electrodes.
The direction of conduction of the unidirectionally conducting devices minimizes current flow between the input points and the cross-coupled electrodes thereby substantially isolating the input points from the cross-coupled electrodes.
During the start of a memory read cycle, the memory start (MS) line goes to 0 volts bringing the gate of transistor T3 below threshold, thereby turning it off.
The output nodes A and B are charged through depletion devices T4 and T5.
The output nodes are now balanced.
As the cell is addressed, a small differential signal is established between the two bit lines (bit 0 and bit 1).
This differential is translated to the output nodes through isolation devices T6 and T7.
The MS terminal is now brought to a positive voltage VH causing T3 to conduct bringing the sources of cross-coupled transistors T1 and T2 near ground