Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Fault Detection Semiconductor-integrated-circuit-boundary-scan-test-with-multiplexed-node-selection

 Testing of digital-to-analog converters
In general, a technique for testing digital-to-analog converters includes providing a set of ...


 Method and apparatus for failure detection utilizing functional test vectors and scan mode
OF THE INVENTION A method and software for failure detection of logic nodes within an integrated ...


 Testing apparatus embedded in scribe line and a method thereof
The object of the present invention therefore is to provide a testing apparatus embedded in a ...


 Method and apparatus for light-controlled circuit characterization
Principles of the present invention provide light-controlled circuit characterization techniques. F...


 Method and system for instrumenting simulation models
It is therefore an object of the invention to provide a method and system for interactively ...


 Facilitating simulation of a model within a distributed environment
The shortcomings of the prior art are overcome and additional advantages are provided through the ...


 Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions
The aforementioned and other features are accomplished, according to the present invention, by ...


 Hardware instruction scheduler for short execution unit latencies
In accordance with the present invention an apparatus for scheduling a stream of instructions per ...


 Multi-threading for a processor utilizing a replay queue
I. Introduction According to an embodiment of the present invention, a processor is provided that ...


 Checkpointing of register file
The invention in one aspect includes methodology to perform an extra read from a register file ...


 Semiconductor integrated circuit boundary scan test with multiplexed node selection

Details
Inventors: Imai, Kiyoshi; Tsuji, Toshiaki; Takada, Taku; Taguchi, Seiichi;
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP)
Primary Examiner: Williams; Howard L.
Assistant Examiner:
Attorney, Agent or Firm: Willian Brinks Olds Hofer Gilson & Lione

A semiconductor integrated circuit having a test circuit built therein is disclosed which consists of an A/D converter to be connected to a peripheral circuit, a digital circuit connected to the A/D converter, a digital signal switching device for selectively connecting to the output of the A/D converter and that of the digital circuit, and a boundary scan output circuit connected to the output of the digital signal switching device, wherein the digital signal switching device connects the A/D converter to the boundary scan output circuit in a normal mode, while the signal fetched in the boundary scan output circuit is outputted therefrom in test mode. Semiconductor integrated circuits having an analog circuit built therein and an analog integrated circuit in which a test circuit is built-in are also disclosed.

DETAILED DESCRIPTION The object of the present invention is therefore to provide a semiconductor integrated circuit having a test circuit built therein to facilitate the board test of massproduced printed circuit boards having both analog and digital circuits thereon.
In order to achieve the object, the present invention provides a semiconductor integrated circuit comprising a digital circuit and an A/D converter, in which the inputs of digital signal switching devices are outputs of the A/D converter and digital circuit, and boundary scan output circuits are connected to the outputs of the digital signal switching devices.
According to another aspect of the present invention, a semiconductor integrated circuit is provided, which comprises an analog circuit, an A/D converter and a digital circuit, wherein the inputs of an analog signal switching device are outputs of an analog signal input terminal and analog circuit, the inputs of digital signal switching devices are outputs of the A/D converter and digital circuit, and boundary scan output circuits are connected to the outputs of the digital signal switching devices.
The A/D converter is connected to an output of the analog signal switching device, and the digital circuit is connected to outputs of the A/D converter.
According to a yet further aspect of the present invention, a semiconductor integrated circuit is provided, which comprises an analog circuit alone, wherein an analog signal switching device has inputs from analog signal input terminals, an A/D converter is connected to an output of the analog signal switching device, and boundary scan output circuits are connected to the outputs of the A/D converter.
In the aforementioned structure, in a semiconductor integrated circuit comprising a digital circuit and an A/D converter, outputs from the A/D converter are set directly to the boundary scan output circuits by the digital signal switching devices, so that the improper connection of an analog circuit in the periphery of the A/D converter mounted outside the semiconductor integrated circuit is inspected



Related patents
  Testing the integrity of an electrical connection to a device using an onboard controllable signal source
OF THE INVENTION The present invention is directed to systems and a method for testing the integrity of an electrical connection mounted on a circuit assembly using an ...
  Apparatus for I/O leakage self-test in an integrated circuit
According to one embodiment, an integrated circuit is disclosed that includes a first input/output (I/O) circuit and a leakage detection circuit coupled to the first I/O ...
  Mechanism for enabling compliance with the IEEE standard 1149.1 for boundary-scan designs and tests
The present invention provides a mechanism for boundary-scan design and test methodologies applicable to timing-critical high (above 200 MHz) speed clock designs, which ...
  Independent remote computer maintenance device
It is an object of the present invention to provide an independent computing device for diagnosing and repairing a host computer. It is another object of the present ...
  Method, system, and program for diagnosing a computer in a network system
OF THE PREFERRED EMBODIMENTS In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several ...
  System and method for identifying executable diagnostic routines using machine information and diagnostic information in a computer system
FIG. 1 is a diagram illustrating an embodiment of a computer system. FIG. 1 depicts a computer system 100. Computer system 100 includes a processor 110, a chipset 120, ...
  Methods for quantitative analysis by tandem mass spectrometry
Embodiments of the present invention provide methods for deconvoluting contributions of a plurality of analytes utilizing a tandem mass spectrometry, or MS.sup.n signal. ...
  Design-for-testability method for path delay faults and test pattern generation method for path delay faults
OF THE INVENTION First Embodiment A first embodiment of the present invention relates to a design-for-testability method of changing the design of an integrated circuit ...
  Method for optimizing test development for digital circuits
The present invention provides test patterns to detect timing related failures in large digital ICs, to rapidly detect least slack paths. Such digital ICs typically ...
  Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
OF THE INVENTION The present invention provides a switchable pull-up circuit particularly well-suited for use in IDDQ testing of integrated circuits having input and ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved