 Programmable, reconfigurable DSP implementation of a Reed-Solomon encoder/decoder |
| This invention relates to programmable, reconfigurable implementations of Reed-Solomon encoder/... |
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| Optimizing repeaters positioning along interconnects |
| A preferred embodiment of the present invention provides an aspect of interconnect design for ... |
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| Method and apparatus for placing repeaters in a network of an integrated circuit |
| OF THE PREFERRED EMBODIMENT(S) FIG. 1 is a schematic diagram of a network or net 100 that is used ... |
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| Parasitic element extraction apparatus |
| It is an object of the present invention to solve at least the problems in the conventional ... |
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| Bist architecture for measurement of integrated circuit delays |
| The IC to be tested is provided with, in one embodiment, a two-wire test bus, which passes near ... |
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| Oscillator for measuring on-chip delays |
| FIG. 2 is a schematic diagram of an oscillator 200 configured, in accordance with the invention, ... |
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| Method and system for measuring signal propagation delays using ring oscillators |
| FIG. 2 is a schematic diagram of a conventional tester 200 connected to an FPGA 210 that has been ... |
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| Monitor TEG test circuit |
| OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals ... |
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Semiconductor memory device having even and odd numbered bank memories
| Details |
Inventors: Kai, Naoyuki;
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)
Primary Examiner: Fears; Terrell W.
Assistant Examiner: Koval; Melissa J.
Attorney, Agent or Firm: Finnegan, Henderson, Farabow, Garrett & Dunner
A semiconductor memory device comprises an address signal generator for generating address signals including row and column address signals, and an additional address signal to indicate if the column address is even- or odd-numbered; even- and odd-numbered bank memories with a plurality of word areas each including n bit areas; row decoder which in response to a row address signal, specifies the row address position in the even- or odd-numbered bank memory; and a column decoder which in response to the address signal, specifies the column address positions in the even- and odd-numbered bank memories. The column decoder responds to the address signal representing the column address 2j or (2j+1), to specify the column address position [2j] or [2j+2] in the even-numbered memory, and at the same time specifies the column address position [2j+1] in the odd-numbered bank memory. |
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DETAILED DESCRIPTION An object of this ivention is to provide a semiconductor memory device which can simultaneously access a plurality of bits of a word data defined by bit area boundaries, and increases the data-processing speed.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly desribed herein, the semiconductor memory device of this invention comprises an address signal generating circuit for generating address signals including row and column address signals and an additional address signal to indicate if the column address is even-or odd-numbered; even and odd numbered bank memories each having a plurality of word areas and each word area including n bit areas; a row decoder connected to said address signal generating circuit and to said even- and odd-numbered bank memories for specifying the row address positions of the even-numbered and odd-numbered bank memories means in response to the row address signal from the address signal generating circuit; a column decoder connected to said address signal generating circuit and to said even- and odd-numbered bank memories, and which responds to the column and additional address signals to specify respectively the column address position (2j) or (2j+2) in the even-numbered bank memory and the column address location (2j+1) in the odd-numbered bank memory when said column and additional address signals indicate column address (2j) or (2j+1); a control data generating circuit for generating control data representing the amount of data rotation corresponding to the number of bits less than 2n bits; and a data rotator connected to the column decoder via a number (2n) bit lines and to said control data generating circuit, and in accordance with the control data from said control data generating circuit, said data rotator selectively connecting 2n bit lines connected to the column decoder, to n input/output bit lines, thereby permitting n-bit data to be transferred between said even and odd-numbered bank memories and said n input/output bit lines via said data rotator
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Fault Detection 
