Semiconductor memory device having redundant circuit

DETAILED DESCRIPTION Accordingly, a first object of this invention is to provide a semiconductor memory device capable of enhancing the access speed.
A second object of this invention is to provide a semiconductor memory device capable of effecting the stable operation.
A third object of this invention is to provide a semiconductor memory device whose current consumption is small.
The above first to third objects of this invention can be attained by a semiconductor memory device comprising a main memory cell array having memory cells arranged in a matrix form; main word lines each connected to those of the memory cells of the main memory cell array which are arranged on a corresponding row; a spare memory cell array having spare memory cells arranged in a matrix form, the spare memory cells of the same number as the memory cells connected to one main word line being arranged on each row; spare word lines each connected to those of the spare memory cells of the spare memory cell array which are arranged on a corresponding row; a spare decoder having a defective row address programmed therein when at least one of the memory cells of the main memory cell array or at least one of the main word lines becomes defective, comparing the programmed defective row address with an input row address signal to check whether or not the compared addresses coincide with each other, outputting a control signal corresponding to the coincidence/non-coincidence of the compared row addresses, and outputting a first partial decode signal of the input address signal when the compared addresses coincide with each other; a spare row decoder for receiving the first partial decode signal and selectively driving the spare word lines; a row partial decoder for receiving the input row address signal and the control signal and outputting a second partial decode signal of the input row address signal when the control signal indicates the non-coincidence of the addresses; and a main row decoder for receiving the second partial decode output and selectively driving the main word lines