Semiconductor memory device having split operation and capable of reducing power supply noise

DETAILED DESCRIPTION An object of the present invention is to provide a semiconductor memory device that effectively overcomes the problem associated with the prior art technology that was described above; viz, increasing power supply noise that accompanies greater levels of chip integration density.
In order to overcome the above-mentioned drawback of conventional technologies, a semiconductor memory device according to the invention comprises: a plurality of groups of memory cell blocks capable of split operation, each of said groups of memory cell blocks being provided with a plurality of memory cell blocks having predecoders receiving predecoder input signals; a predecoder input signal generator responsive to a group select signal which causes said groups of memory cell blocks to perform split operation, for selectively activating the groups of predecoder input signal lines, and setting the predecoder input signal lines for the selected group of memory cell block to either the high level or the low level depending the external address information; and a clamping means responsive to said group select signal for clamping substantially half of the predecoder input signal lines for the group of memory cell blocks that are not selected by said group select signal, to the high level, and the remaining half to the low level.
As a semiconductor memory device according to the present invention is configured as described above, on the basis of the group select signal, the predecoder input signal generator selects the group of predecoder input signal lines for the group of memory cell blocks have been selected by the group select signal, activates it, and sets the group of input signal lines for the selected group at either the high level or the low level in accordance with the external address information.
Then, the predecoders in the selected memory cell block group predecode the high-low binary logic of the input predecoder input signals, for selection of the memory cells.
Meanwhile, the clamping means clamps approximately half of the predecoder input signal lines for the unselected group at the high level and the remaining half at the low level