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Fault tolerant system employing majority voting
An object of the present invention is to provide a fault tolerant system which is able to select and output a normal signal whenever there is at least one normal ...
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High speed bus with virtual memory data transfer capability using virtual address/data lines
An improved high speed bus with virtual memory capability is disclosed. The bus has particular application in computer systems which employ peripheral devices. The bus ...
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Synchronizing two processors as an integral part of fault detection
What is claimed is: 1. A central processor unit including a fault detector means for detecting a fault in said central processor unit, said central processor unit ...
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Byzantine resilient fault tolerant shared memory data processing system
What is claimed is: 1. A fault tolerant data processing system for providing single fault Byzantine resilience, said system comprising: a plurality of fault containment ...
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Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems
It is the object of the current invention to provide a multiprocessor programmable interrupt controller (MPIC) system including, but not limited to, the following ...
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Protocol for interrupt bus arbitration in a multi-processor system
One object of the present invention is to provide for a multi-processor programmable interrupt controller (MPIC) system that uses an integrated circuit chip ...
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Multiprocessor computer backlane bus
OF THE PREFERRED EMBODIMENTS The following detailed description describes the logical, electrical, and connector specifications of Pyramid Technology Corporation's R-B ...
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Digital data processing methods and apparatus for fault detection and fault tolerance
The invention provides, in one aspect, a digital data processing device that includes a bus for transmitting signals (e.g., data and/or address information) between ...
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Method and apparatus for allocating display memory and main memory employing access request arbitration and buffer control
The present invention, generally speaking, provides a low-cost, moderate performance small computer system by allowing a single sharable block of memory to be ...
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Register set reordering for a graphics processor based upon the type of primitive to be rendered
The present invention provides a technique and protocol for reordering the register sets comprising the register file based upon the type of primitive to be rendered. T...
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