Serial scan chain architecture for a data processing system and method of operation

DETAILED DESCRIPTION What is claimed is: 1.
A data processor having a scan chain architecture, the scan chain architecture comprising: a plurality of scan chains wherein each scan chain in the plurality of scan chains has a plurality of serially connected storage elements, each scan chain having a first storage element which has a scan input and a last storage element which has a scan output; a multiplexer having a plurality of inputs wherein each input in the plurality of inputs is coupled to one scan output from the plurality of scan chains, the multiplexer having a multiplexer output wherein the multiplexer output is selectively coupled to one of the inputs in the plurality of inputs via the multiplexer; a demultiplexer having a plurality of outputs wherein each output in the plurality of outputs is coupled to one scan input from the plurality of scan chains, the demultiplexer having a demultiplexer input wherein the demultiplexer input is selectively coupled to one output in the plurality of outputs via the demultiplexer; and an output scan chain having an input coupled to the output of the multiplexer and an output coupled to an output terminal of the data processor, the multiplexer serially coupling the output scan chain to a selected one of the plurality of scan chains to form a total scan chain comprising the selected one of the plurality of scan chains and the output scan chain.
2.
The data processor of claim 1 wherein one of the scan chains in the plurality of scan chains is used to serially scan binary data for a circuit module selected from a group consisting of: an operand cache unit, and instruction cache unit, a bus interface unit, an integer processing unit, and a floating point unit.
3.
The data processor of claim 1 wherein the demultiplexer is part of a test controller which receives a plurality of test address signals wherein the plurality of test address signals selects one scan chain in the plurality of scan chains to receive a serial bit stream via a serial data input coupled to the demultiplexer input