Signal detection circuit using a plurality of delay stages with edge detection logic

DETAILED DESCRIPTION What is claimed is: 1.
A circuit for detecting a digital signal, comprising: a plurality of delay stages coupled in series; edge detection logic coupled to an input of a delay stage from among said delay stages and an output of the delay stage for outputting a signal indicative of a prescribed characteristic of the digital signal; and a counter coupled to the edge detection logic for counting, in response to a master clock signal, the prescribed characteristic of the digital signal based on the signal output from the edge detection logic.
2.
The circuit of claim 1, wherein the prescribed characteristic of the digital signal is an edge in the digital signal.
3.
The circuit of claim 1, wherein the delay stage includes a non-inverting delay stage.
4.
The circuit of claim 3, wherein the edge detection logic includes an XOR gate coupled to the input and output of the non-inverting delay stage.
5.
The circuit of claim 3, wherein the edge detection logic includes an inverter coupled to the output of the non-inverting delay stage.
6.
The circuit of claim 5, wherein the edge detection logic further includes an AND gate coupled to an output of the inverter and the input of the non-inverting delay stage.
7.
The circuit of claim 5, wherein the edge detection logic further includes a NOR gate coupled to an output of the inverter and the input of the non-inverting delay stage.
8.
The circuit of claim 3, wherein the edge detection logic includes an inverter coupled to the input of the non-inverting delay stage.
9.
The circuit of claim 8, wherein the edge detection logic further includes an AND gate coupled to an output of the inverter and the output of the non-inverting delay stage.
10.
The circuit of claim 8, wherein the edge detection logic further includes a NOR gate coupled to an output of the inverter and the output of the non-inverting delay stage.
11.
The circuit of claim 3, wherein the non-inverting delay stage includes a pair of inverting delay stages coupled in series.
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