Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Fault Detection Standby-current-detecting-circuit-for-use-in-a-semiconductor-memory-device-and-method-thereof

 Standby current detecting circuit for use in a semiconductor memory device and method thereof

Details
Inventors: Han, Jin-Man; Yoo, Jei-Hwan;
Assignee: Samsung Electronics, Co., Ltd. (Suwon, KR)
Primary Examiner: Zarabian; A.
Assistant Examiner:
Attorney, Agent or Firm: Marger, Johnson, McCollom, & Stolowitz P.C.

A standby current detecting circuit for use in a semiconductor memory device and method thereof are described. The memory device has a plurality of memory cells arranged at crossing points of a plurality of word lines and a plurality of bit lines. A plurality of switches are associated with each memory cell. A current path supplies current to each memory cell through the switch associated with each memory cell. A plurality of decoders are provided with each decoder for detecting a standby current supplied on one such current path for the memory cell. Each decoder includes control logic for selectively opening and isolating the switch associated with the memory cell in a standby current detection mode.

DETAILED DESCRIPTION Therefore, it is an object of the present invention to provide a standby current detecting circuit and method for detecting where within a semiconductor memory device a short circuit is generated.
An embodiment of the present invention is a standby current detecting circuit for use in a semiconductor memory device.
The memory device comprises a plurality of memory cells arranged at crossing points of a plurality of word lines and a plurality of bit lines.
A plurality of switches are associated with each memory cell.
A current path supplies current to each memory cell through the switch associated with each memory cell.
A plurality of decoders are provided with each decoder for detecting a standby current supplied on one such current path for the memory cell.
Each decoder includes control logic for selectively opening and isolating the switch associated with the memory cell in a standby current detection mode.
A further embodiment of the present invention is a method for locating a malfunctioning memory cell in a semiconductor memory device.
The memory device comprises a plurality of the memory cells and a plurality of decoders.
Each memory cell comprises a switch for isolating an associated current path to the memory cell.
Each decoder is associated with one such memory cell and includes a detector for detecting a standby current supplied on one such current path for the memory cell.
A fraction of the memory cells in the memory device are selected.
The current path to each of the memory cells in the fraction of the memory cells selected is opened.
The standby current flowing into the fraction of the memory cells with open current paths is sensed.
A further fraction of the memory cells in the memory device not selected in the set of selecting is chosen if the standby current is not sensed as flowing into the fraction of the memory cells.
The steps of selecting, opening, sensing and choosing are repeated using the fraction of the memory cells or the further fraction of the memory cells into which the standby current is sensed as flowing into until a single memory cell is selected



Related patents
  Process and device for checking substrate wafers
Since a defect counting process, particularly a counting process carried out by an operator, is extremely time-consuming and tiring, one of the objects of the present ...
  Synchro-to-digital converter
Accordingly, a primary object of the present invention is to provide a synchro-to-digital converter whereby digital values representing an absolute angular position of ...
  Duty cycle control apparatus
What is claimed is: 1. Apparatus for controlling the duty cycle of an input signal having a period, said apparatus comprising: control means for controlling the ...
  Signal level comparing circuit
It is accordingly an object of this invention to provide a signal level comparing circuit which can process an input signal whose maximum voltage level stands higher ...
  Circuit arrangement for correcting slip errors in pcm receivers
I claim: 1. In a receiver for binary code words including information bits and redundancy bits to enable detection of an error, in combination: a line carrying incoming ...
  Redundant clock system utilizing nonsynchronous oscillators
In accordance with the present invention, there is provided a clock system with two nonsynchronized digital clocks, each having a select circuit for selecting the output ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved