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Home Fault Detection State-metric-memory-arrangement-for-a-viterbi-decoder

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 State metric memory arrangement for a viterbi decoder

Details
Inventors: Porter, Jeffrey A.;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Atkinson; Charles E.
Assistant Examiner: Baker; Stephen M.
Attorney, Agent or Firm: Bogacz; Frank J.

An improved memory utilization arrangement for a VITERBI decoder which allows the amount of memory required for storing state metrics to be minimized. Both old and new state metrics are required to be stored. This scheme utilizes memory locations for which old metrics have been previously read for storing the newly calculated metrics. In one implementation of this invention, a barrel shifter is used to calculate the address at which to store and retrieve the appropriate metrics. Another implementation employs a shift register with a shifting and inserting operation to align the metrics in the proper order and at the same time store the new metrics for subsequent calculations. As a result of the saving of memory, the amount of memory and power consumption are reduced substantially.

DETAILED DESCRIPTION In accomplishing the object of the present invention, a novel state metric memory apparatus is shown.
In one embodiment, a state metric memory arrangement for a VITERBI decoder includes a register for storing a plurality of state metrics.
This register serially shifts each of the plurality of state metrics a predefined number of times.
Next, a serial to parallel converter is connected to the register.
The serial to parallel converter forms required pairs of the state metrics.
These required pairs of state are ones required for calculation of new state metrics.
An add-compare-select circuit is connected to the serial to parallel converter and to the register.
The add-compare-select circuit calculates the new state metrics from the required pairs of state metrics.
Further, the add-compare-select circuit transmits the newly calculated state metrics to the register in a particular order for storage therein.
Lastly, the register operates to store certain ones of the newly calculated metrics interleaved with others of the newly calculated state metrics.
In another embodiment, the state metric memory arrangement for a VITERBI decoder includes a state counter.
The state counter sequentially generates a series of states indicating which of the state metrics are required for new calculation.
An address generator is connected to the state counter.
The address generator produces a physical address for retrieving the required state metrics for calculation.
A memory is connected to the state counter and to the address generator.
The memory is operated in response to the state counter and to the address generator to store and to retrieve previously stored state metrics.
A state metric calculator is connected to the memory.
The state metric calculator operates in response to the retrieved state metrics to calculate new state metrics.
The memory operates in response to the address generator and to the state metric calculator to store the newly calculated state metrics at a location indicated by the address generator, ones vacant due to the retrieval operation



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