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Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
| Details |
Inventors: Colwell, Michael; Rajsuman, Rochit; Abrishami, Ray; Sarkari, Zarir B.;
Assignee: LSI Logic Corporation (Milpitas, CA)
Primary Examiner: Karlsen; Ernest F.
Assistant Examiner:
Attorney, Agent or Firm: Oppenheimer Poms Smith
An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller. |
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DETAILED DESCRIPTION OF THE INVENTION The present invention provides a switchable pull-up circuit particularly well-suited for use in IDDQ testing of integrated circuits having input and output signal lines with pull-ups.
It has been determined that significant improvements in IDDQ testing fault coverage are obtained by incorporating controllable switching capability into pull-ups and pull-downs.
Although the following detailed description is directed to the use of a switchable pull-up circuit in an integrated circuit having one or more signal lines pulled up to a common drain voltage source through a pull-up mechanism comprising a FET, it will be apparent that man, alternative implementations are also possible.
For example, the general principles of the present invention could also be applied to integrated circuit signal lines which are pulled down to ground or a negative voltage potential (pull-down).
It should therefore be understood that the terms "pull" and "pull-up" as used generically herein are intended to include any device which is used to connect a signal line to a positive, negative or ground voltage potential.
These terms as used herein thus encompass devices often otherwise referred to as pull-downs.
Furthermore, the utility of the present invention is not limited to IDDQ testing but is instead applicable to any situation in which it is desirable to control connection of a signal line to a voltage potential.
The term "pull circuit" can be used to generically denote a pull-up circuit or a pull-down circuit.
Alternative applications include reducing stand-by current on unused signal lines which include a pull-up, and providing a controllable interface to external circuitry.
An exemplary embodiment of the switchable pull-up circuit of the present invention applied to an integrated circuit input is shown in FIG.
2.
The exemplary integrated circuit input 20 includes a signal line 22 connected through a switchable pull-up circuit 21 to a voltage source 26.
In this exemplary embodiment voltage source 26 is preferably the V
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Fault Detection 
