 Data stream smoothing using a FIFO memory |
| The present invention is directed to the use of a FIFO memory for communicating data from a DRAM to ... |
|
| Semiconductor memory device having redundant circuit |
| Accordingly, a first object of this invention is to provide a semiconductor memory device capable ... |
|
| Redundant address decoder |
| Accordingly, an object of the present invention is to provide a redundant address decoder which can ... |
|
| Automatic transition charge pump for nonvolatile memories |
| Generally, the present invention provides a high voltage charge pump for programming a non-voltage ... |
|
| High speed static BiCMOS memory with dual read ports |
| A memory includes a plurality of cells with each cell containing a pair of cross-coupled N-channel ... |
|
| Flexible redundancy architecture and fuse download scheme |
| What is claimed is: 1. In an integrated circuit comprising a plurality of circuit elements, some of ... |
|
| Flexibilitiy for column redundancy in a divided array architecture |
| The present invention relates to an apparatus and method for implementing flexible redundancy ... |
|
| Row redundancy block architecture |
| It is therefore an object of the present invention to provide a redundancy block architecture which ... |
|
| Shortened timeout period during frame retry in a communication link |
| The present invention is embodied in a system and method for asynchronously transmitting data ... |
|
|
Synchronizing two processors as an integral part of fault detection
| Details |
Inventors: McDonald, Keith M.;
Assignee: AG Communication Systems Corporation (Phoenix, AZ)
Primary Examiner: Beausoliel, Jr.; Robert W.
Assistant Examiner: Chung; Phung
Attorney, Agent or Firm: Baca; Anthony J.
A central processing unit arrangement for detecting a fault in a central processing unit system that includes a master processor and a slave processor. Master and slave processors are resynchronized at every bus cycle by conditioning the processors' READY signal with the ADS (address status) signals from each processor (ADS indicates that an access cycle has begun and a valid address is present on the address bus). This method of synchronization was selected over the more traditional method of lock-step, which was deemed impractical to implement given the timing constraints of a high speed bus. Also, the dual processors may not always begin their respective bus cycles on the same clock. In addition, it is necessary to synchronize processors for the first instruction fetch following a reset, because the time of completion of an internal self-test may not be deterministic. After both ADS signals are received, the status of the master and slave buses are compared and a fault is detected if the buses are different. If a predetermined amount of time passes before both ADS signals are received then the processors are signaled to continue with the cycle. Because the processors are no longer synchronized, the buses will miscompare, thereby detecting a fault. Additional fault detection measures can be taken such as parity, checksum and EDAC. |
|
DETAILED DESCRIPTION What is claimed is: 1.
A central processor unit including a fault detector means for detecting a fault in said central processor unit, said central processor unit comprising: a master processor means for providing a first address bus, a first data bus and a first address stable signal, said first address stable signal being active when said first address bus is stable, after said master processor means generates said first address stable signal said master processor means waits until a master ready signal is received; a slave processor mean for providing a second address bus, a second data bus and a second address stable signal, said second address stable signal being active when said second address bus is stable, after said slave processor means generates said second address stable signal said slave processor means waits until a slave ready signal is received; a ready synchronizer means for receiving said first address stable signal from said master processor means and said second address stable signal from said slave processor means, subsequent to receiving both said first address stable signal and said second address stable signal said ready synchronizer means generates a synchronized ready signal, said synchronized ready signal being transmitted to said master processor means and said slave processor means, said master processor means receiving said synchronized ready signal as said master ready signal and said slave processor means receiving said synchronized ready signal as said slave ready signal; and a comparator means for receiving said first address bus, said first data bus, said second address bus, said second data bus and said synchronized ready signal, said comparator means compares said first address bus with said second address bus, and, said first data bus with said second data bus when said synchronized ready signal is received, said comparator means generates an alarm signal when said first address bus and said second address bus are different, said comparator means generates said alarm signal when said first data bus and said second data bus are different, said fault being detected in said central processor unit when said alarm signal is generated
|
| Related patents |
|
|
Byzantine resilient fault tolerant shared memory data processing system
What is claimed is: 1. A fault tolerant data processing system for providing single fault Byzantine resilience, said system comprising: a plurality of fault containment ...
|
|
|
Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems
It is the object of the current invention to provide a multiprocessor programmable interrupt controller (MPIC) system including, but not limited to, the following ...
|
|
|
Protocol for interrupt bus arbitration in a multi-processor system
One object of the present invention is to provide for a multi-processor programmable interrupt controller (MPIC) system that uses an integrated circuit chip ...
|
|
|
Multiprocessor computer backlane bus
OF THE PREFERRED EMBODIMENTS The following detailed description describes the logical, electrical, and connector specifications of Pyramid Technology Corporation's R-B ...
|
|
|
Digital data processing methods and apparatus for fault detection and fault tolerance
The invention provides, in one aspect, a digital data processing device that includes a bus for transmitting signals (e.g., data and/or address information) between ...
|
|
|
Method and apparatus for allocating display memory and main memory employing access request arbitration and buffer control
The present invention, generally speaking, provides a low-cost, moderate performance small computer system by allowing a single sharable block of memory to be ...
|
|
|
Register set reordering for a graphics processor based upon the type of primitive to be rendered
The present invention provides a technique and protocol for reordering the register sets comprising the register file based upon the type of primitive to be rendered. T...
|
|
|
Preamplification method and apparatus for dram sense amplifiers
An object of the present invention is to improve reliability of read out in DRAM. Another object of the present invention is to increase the potential difference applied ...
|
|
|
Semiconductor memory device
It is an object of the present invention to provide a semiconductor memory device including a FAMOS transistor type redundancy decoder circuit suitable for practical use....
|
|
|
Semiconductor device
It is accordingly the object of this invention to provide a reliable semiconductor device which enables binary data to be stored in a nonvolatile memory element without ...
|
|
|
Fault Detection 
