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System, IC chip, on-chip test structure, and corresponding method for modeling one or more target interconnect capacitances
| Details |
Inventors: Chen, James C.;
Assignee: BTA Technology, Inc. (San Jose, CA)
Primary Examiner: Metjahic; Safet
Assistant Examiner: Nguyen; Jimmy
Attorney, Agent or Firm: Caserza; Steven F. Flehr Hohbach Test Albritton & Herbert LLP
A system, an IC chip, a test structure formed on the IC chip, and a corresponding method for modeling one or more target interconnect capacitances is disclosed. The test structure comprises an interconnect configuration comprising a test interconnect and one or more target interconnects. The interconnect configuration has, for each target interconnect, a corresponding target interconnect capacitance between the test interconnect and the target interconnect. The test structure also comprises a test interconnect charging circuit connected to the test interconnect. The test interconnect charging circuit is configured to place a test charge on the test interconnect. The test structure further comprises one or more target interconnect charging circuits. Each target interconnect charging circuit is connected to a corresponding target interconnect. Each target interconnect charging circuit is configured to draw a target interconnect charging current from the corresponding target interconnect in response to the test charge. This places an opposite charge on the corresponding target interconnect that is induced by the corresponding target interconnect capacitance. As a result, a measurement of the corresponding target interconnect capacitance may be computed by making a measurement of the target interconnect charging current with a current meter of the system. |
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DETAILED DESCRIPTION In summary, the present invention comprises a system, an IC chip, a test structure formed on the IC chip, and a corresponding method for modeling one or more target interconnect capacitances.
The test structure comprises an interconnect configuration formed on the IC chip.
The interconnect configuration comprises a test interconnect and one or more target interconnects.
The interconnect configuration has, for each target interconnect, a corresponding target interconnect capacitance between the test interconnect and the target interconnect.
The test structure also comprises a test interconnect charging circuit formed on the IC chip and connected to the test interconnect.
The test interconnect charging circuit is configured to place a test charge on the test interconnect.
The test structure further comprises one or more target interconnect charging circuits.
Each target interconnect charging circuit is formed on the IC chip and connected to a corresponding target interconnect.
Each target interconnect charging circuit is configured to draw a target interconnect charging current from the corresponding target interconnect in response to the test charge.
This places an opposite charge on the corresponding target interconnect that is induced by the corresponding target interconnect capacitance.
A measurement of the target interconnect charging current can be made with a current meter of the system.
From this measurement, a measurement of the corresponding target interconnect capacitance may be computed.
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