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System for coding system
| Details |
Inventors: Herzberg, Hanan;
Assignee:
Primary Examiner: Baker; Stephen M.
Assistant Examiner:
Attorney, Agent or Firm: Thomas, Kayden, Horstemeyer & Risley
A method and apparatus for coding an information signal are provided. In accordance with one aspect of the invention, the method includes the step of encoding all or a portion of the information signal with a first encoder to generate a first set of redundant bits (preferably r.sub.1 bits). The method further includes the step of passing a portion of (and possibly all) the information signal through a structured interleaver to generate an interleaved signal. The method then encodes all or a portion of the interleaved signal with a second encoder to generate a second set of redundant bits (preferably r.sub.2 bits). Finally, the method includes the step of concatenating the information signal, the first set of redundant bits, and the second set of redundant bits to form an encoded output signal. A significant aspect of the present invention is the use of a structured interleaver in the encoder. It has been found that the structured interleaver provides a low bit error rate, and a much shorter length (and thus delay) than random interleavers. The foregoing concept apply equally to multi-level coding, wherein a parallel concatenated code defined by a structured interleaver may be utilized as a constituent code in a multi-level encoder. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Having summarized the present invention, reference will now be made in detail to the description of the invention as illustrated in the drawings. While the invention will be described in connection with these drawings, there is no intent to limit it to the embodiment or embodiments disclosed therein. On the contrary, the intent is to cover all alternatives, modifications and equivalents included within the spirit and scope of the invention as defined by the appended claims. Background on Multilevel Encoding and Multistage Decoding Before discussing the preferred embodiment of the present invention, a background on multilevel encoding and multistage decoding will first be provided. In this regard, reference is made to FIG. 1, which is a block diagram illustrating the structure of a simple multilevel encoder 10. The illustrated encoder is an L level encoder having a serial to parallel converter 12 at the front end. As is known, the serial to parallel converter 12 includes an input and a plurality of outputs. Most of the outputs are associated with, and directed to an encoder 14, 16, 17. Each of the encoders 14, 16, 17 will receive one or more bits for encoding, and output the encoded bits to a symbol selector 18. As illustrated, uncoded bits may be communicated directly from the serial to parallel converter 12 to the symbol selector 18 across one or more lines 19. Multilevel coding has been recognized as an efficient way of combining error correction coding with modulation. Multilevel coding, is generally a combination of several error correction codes applied to subsets of some signal constellation. As is known, a typical code of this kind is, based on a set S. sub. 0 and an L level partition chain S. sub. 0 /S. sub. 1 . . . /S. sub. L. In the multilevel encoder 10 of FIG. 1, the sequence of bits associated with the partition S. sub. i-1 /S. sub. i is a codeword of the binary code C. sub. i (n. sub. i, k. sub. i), and E. sub. i is the corresponding encoder. The multilevel code may be made up of convolutional component codes, block codes, or a combination thereof An important parameter of a coded modulation scheme is the computational complexity of the decoder
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