 Selectively updateable mapped data storage system |
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| Data storage system and method employing a write-ahead hash log |
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| Method to ensure data integrity in a telecommunications network |
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| Method and circuitry for generating r-bit parallel CRC code for an l-bit data source |
| Therefore, the main objective of the present invention is to provide a method and circuitry for ... |
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| Cyclic code check bits generation and error correction using sum of remainders |
| In accordance with the present invention check bits for a cyclic code are generated for a binary ... |
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| Method and apparatus for G.706 frame alignment and CRC procedure test tool |
| In order to comply with CCITT G.706 recommendation, a device has to satisfy a series of test cases ... |
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System for operating input, processing and output units in parallel and using DMA circuit for successively transferring data through the three units via an internal memory
| Details |
Inventors: Nakatsuji, Fumio; Maeda, Toshinori; Kamiyama, Hiroshi;
Assignee: Matsushita Electric Industrial, Co. (JP)
Primary Examiner: Lee; Thomas C.
Assistant Examiner: Gossom; Twanna
Attorney, Agent or Firm: Price, Gess & Ubell
A data input-output device includes a single memory, an input interface unit for storing data in the memory, an operation unit for fetching the data from the memory, for performing operations on the data, and for updating the data in the memory when necessary, an output interface unit for transmitting the data in the memory that has been operated on by the operation unit to outside of the device, and a bus control unit for setting a priority for each of these units and for controlling memory access by these units according to the priorities every time a predetermined number of bytes of data is transferred. |
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DETAILED DESCRIPTION It is accordingly an object of the present invention to provide a data input-output device that does not need to include different memories for storing data input at a first transmission rate and data to be output at a second transmission rate.
Another object of the present invention is to provide a data input-output device that outputs data after performing an error correction process on the input data without ineffective waiting time.
The above-mentioned first object is achieved by a data input-output device that performs operations on data input from a first device located outside thereof, and outputs the data to a second device located outside thereof including: an input unit for continually receiving data from the first device; an operation unit for performing an operation on the data; an output unit for outputting the data to the second device; a memory for storing the data; a memory bus for connecting the input unit, the operation unit, and the output unit with the memory; a first data transfer unit for performing first DMA (direct memory access) transfer which transfers the data from the input unit to the memory; a second data transfer unit for performing second DMA transfer which, when the first data transfer unit has completed the first DMA transfer for a first predetermined amount of data, transfers the data that was stored by the first DMA transfer from an area in the memory to the operation unit as the data for the operation; a third data transfer unit for performing third DMA transfer which, when the operation unit has completed the operation for the first predetermined amount of data, transfers the data operated on by the operation unit from the area in the memory to the output unit; and a data transfer control unit for performing control so that at any given time, data transfer is performed by the first data transfer unit, the second data transfer unit, or the third data transfer unit, wherein the input unit, the operation unit, and the output unit operate independently in parallel
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