TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports

DETAILED DESCRIPTION In accordance with the present invention, selection and testing of multiple TAP'ed cores within a large integrated circuit can be performed without adding test interface pins beyond those specified by the IEEE 1149.
1 standard, and without modifying the TAP design of the cores.
This is accomplished by a novel design of the Tap Linking Module, referred to hereafter as TLM, which eliminates the need to redesign core TAPs.
Briefly, the present invention enables an IEEE 1149.
1 test pin interface on an integrated circuit to access any number of standard TAPs within an integrated circuit by providing a TLM that is operable to switch the TAPs to the test pins in response to 1149.
1 scan operations.
No design modifications are required on TAPs used with the present invention.
It is an object of the present invention to provide the following features.
(1) Provide a TLM architecture for integrated circuits which operates to enable and disable 1149.
1 scan access to TAPs without having to modify the design of TAPs.
Hence, the invention can be used on legacy cores having non-modifiable TAPs.
(2) Maintain independent development of scan test patterns specific to each embedded core such that the scan test patterns may be directly applied to the core independent of other cores within the integrated circuit.
Hence, maintenance and application of core scan test patterns is simplified.
(3) Allow for maximizing the scan test frequency (i.
e.
TCK frequencies) to each core independent of other cores whose scan test frequency may be less than the scan test frequency of the core being tested.
Hence, core test times are reduced.
(4) Ability to re-use, without modification, the test patterns of a core in different integrated circuit designs utilizing the core.
Hence, the ease of scan test pattern re-use between integrated circuits utilizing the same core is realized.
(5) Allow for core test integration to become the simple concatenation of the different re-usable scan test patterns of the different cores serially connected to the TLM