Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Fault Detection Technique-for-generating-single-bit-error-correcting-two-bit-burst-error-detecting-codes

 System for generating test data
A system for generating test data that overcomes these and other problems has a data structure ...


 Diabetes management
According to a first aspect of the present invention there is provided a method of predicting the ...


 Method and apparatus for code translation optimization
OF PREFERRED EMBODIMENTS Generally, the present invention provides a method of optimizing software ...


 Method and computer system for loading objects
To achieve the foregoing objectives, the present invention executes the following steps in a ...


 Graphical design processing apparatus for assessing and modifying design of components
It is therefore an object of the present invention to provide a graphic data processing apparatus ...


 Developers tool for object-oriented programming
The present invention fulfills this need in the art by providing a software developer's tool to ...


 Method and apparatus for storing templates in a component system
The present invention provides a component system in which a number of base applications, i.e. ...


 Method and apparatus for executing tasks by following a linked list of memory packets
OF THE EMBODIMENT FIG. 1 is a high level block diagram of a task flow computing machine 10. M...


 Optical fiber bus controller
FIG. 1 illustrates system 100 which implements the invention. System 100 comprises a number of ...


 Low-latency real-time dispatching in general purpose multiprocessor systems
The present invention provides a method of real-time dispatching in a general purpose ...


 Technique for generating single-bit error-correcting, two-bit burst error-detecting codes

Details
Inventors: Bodnar, Lance M.;
Assignee: TRW Inc. (Redondo Beach, CA)
Primary Examiner: Ton; David
Assistant Examiner:
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus LLP

A method for generating correction codes that can correct a single error and detect two adjacent errors in an information word for a range of (n, k) values, where k denotes the length of the information word in bits and n denotes the length of the coded information word in bits. The method generates a parity check matrix, then multiplies a received word by the parity check matrix to produce a syndrome corresponding to one of two mutually exclusive sets of syndromes if the word contains at least one error. Information in the word is corrected by inverting a bit containing an error if the produced syndrome corresponds to one of the sets of syndromes. An uncorrectable two bit adjacent error is reported if the produced syndrome corresponds to the other of the two sets of syndromes and no error is reported if the produced syndrome contains all zeros.

DETAILED DESCRIPTION A technique for generating correction codes that can correct a single error and detect two adjacent errors in an information word for a range of (n, k) values, where k denotes the length of the information word in bits and n denotes the length of the coded information word in bits, first generates a parity check matrix.
Upon generating the parity check matrix, a received word is multiplied by the parity check matrix to produce a syndrome corresponding to one of two mutually exclusive sets of syndromes if the word contains at least one error, each single bit error in the word corresponding one-to-one with a member of the first of two sets of syndromes and each two bit adjacent error corresponding non-uniquely to a member of the other set of syndromes and a syndrome containing all zeros if the word contains no errors.
The actual information in the word is corrected by inverting a bit containing an error if the produced syndrome corresponds to one of the sets of syndromes and an uncorrectable two bit adjacent error is reported if the produced syndromes corresponds to the other of the two sets of syndromes and no error is reported if the produced syndrome contains all zeros.



Related patents
  Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
The connectivity, connectability and routability of a connection circuit, hereinafter "programmable interconnect matrix" or "PIM," are, as stated above, characteristics ...
  Microprocessor integrated circuit working in internal ROM and external RAM mode
The present invention is aimed at proposing a more efficient, less lengthy and less costly system to develop a microprocessor integrated circuit incorporating the ...
  Method and apparatus for resetting, enabling and freezing a communication device in a diagnostic process
What is claimed is: 1. A communication system, comprising: a host interface for providing a host with access to internal elements of said communication system, and ...
  Code instrumentation system with non intrusive means and cache memory optimization for dynamic monitoring of code segments
Accordingly, the present invention is directed to a system and method for monitoring performance in an information handling system in a minimally intrusive manner. The ...
  Method and apparatus for dynamically optimizing an executable computer program using input data
According to principles of the invention, a method and apparatus for using input data to optimize a computer program for execution on a target computer is provided. I...
  Method and apparatus for profiling indirect procedure calls in a computer program
As discussed in the Background section, the generation of profile data for direct procedure calls is relatively straightforward. However, the generation of profile data ...
  Profile driven optimization of frequently executed paths with inlining of code fragment (one or more lines of code from a child procedure to a parent procedure)
Unfortunately, traditional inlining is often unable to substantially reduce the procedure call overhead of a program where to do so would be highly advantageous. In ...
  Method of, system for, and computer program product for providing efficient utilization of memory hierarchy through code restructuring
The invention disclosed herein comprises a method of, a system for, and an article of manufacture for providing code restructuring based on profiling information and ...
  Software reconfiguration engine
The present invention relates generally to computer system software development and maintenance. More particularly, the invention relates to a reconfiguration system for ...
  Automated validation and verification of computer software
The present invention discloses a method and apparatus for automatic validation and verification of computer software. The software to be tested is first retrieved from ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved