Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same

DETAILED DESCRIPTION The invention may be implemented in a semiconductor memory integrated circuit by providing response circuitry at the ends of signal lines internal to the memory.
Examples of such signal lines include row, or word, lines driven by an address decoder, block select signals driven by an address decoder, control signals produced by control logic, and bit lines in the memory array.
The response circuitry includes a transistor having a conduction path coupled on one end to a bias voltage that is enabled during test mode, and disabled during normal operation, and on another side to a response node; the control electrode is coupled to the far end of the signal line from its drive circuitry.
Accordingly, the voltage at the response node is controlled by the operation of the signal line, such that the transistor is made conductive if the signal line is driven as expected.
According to alternative embodiments of the invention, logical operations may be performed on the response nodes of multiple signal lines.
These logical operations can determine whether adjacent signal lines are shorted to one another, or can perform other operations useful in the diagnosis of a failure.
In addition, the logical combination of multiple response nodes can reduce the test time of the memory device.