Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories

DETAILED DESCRIPTION I claim: 1.
A method of testing memory having a set of M memory locations, said method comprising the steps of: (a) generating a first sequence F.
sub.
k that is pseudorandom; (b) generating a second sequence S.
sub.
k ; one of said first and second sequences is utilized as an address sequence A.
sub.
k and the other of said first and second sequences is utilized as a data sequence D.
sub.
k ; (c) for k=1 to some integer N, storing a kth data word D.
sub.
k in a memory location at address A.
sub.
k ; (d) for a sequence of values of k=1 to some integer L, comparing a value of data actually stored in the memory location at address A.
sub.
k with a value of the data word D.
sub.
k that was to be stored there to determine if there has been an error in storing this data word in this memory location; (e) generating a third sequence T.
sub.
k that is pseudorandom; and repeating steps (c) and (d) with third sequence T.
sub.
k in place of first sequence F.
sub.
k.
2.
A method as in claim 1 wherein N equals M and each of the N data words D.
sub.
k is stored in a uniquely associated address A.
sub.
k, so that every memory location has data stored therein by step (c).
3.
A method as in claim 1 wherein T.
sub.
k =F.
sub.
r where r=(k+q) Mod M for some integer q, whereby the third sequence T.
sub.
k is just an offset version of the first sequence F.
sub.
k : 4.
A method as in claim 1 wherein step (b) comprises the step of generating the second sequence S.
sub.
k with an m-bit counter.
5.
A method as in claim 1 wherein step (a) comprises generating the first sequence F.
sub.
k with a linear feedback shift register.
6.
A method as in claim 5 wherein step (e) comprises generating the third sequence T.
sub.
k with a linear feedback shift register.
7.
A method as in claim 6 wherein the same linear feedback shift register is utilized to generate the first and third sequences.
8.
A method as in claim 7 wherein the first and third sequences are utilized as addresses.
9.
A method as in claim 8 wherein said linear feedback shift register also generates addresses utilized in step (d)