Turbo decoder control for use with a programmable interleaver, variable block length, and multiple code rates

DETAILED DESCRIPTION A control for a turbo decoder utilizing a MAP decoding algorithm comprises an address generator for addressing systematic data symbols, parity data symbols, and systematic likelihood ratios according to a pre-determined memory mapping.
A control signal indicates which of a plurality of component code words comprising a turbo code word is being decoded, each employing the same memory mapping.
The systematic data symbol values are accessed in the order required by the alpha, beta and gamma functions of the MAP decoding algorithm such that interleaving and de-interleaving functions in the MAP decoding algorithm are performed in real-time, i.
e.
, without delay.
The systematic symbol and parity symbol contributions to the gamma function of the MAP decoding algorithm are computed in parallel using parallel channel transition probability look-up tables, such that the channel transition probabilities required in the gamma calculations are accessed at the same rate as the likelihood ratios.
This memory-mapping in combination with other data handling functions (e.
g.
, multiplexing, combinatorial logic and parallel processing) minimizes memory requirements for the turbo decoder and enables the use of programmable interleavers, variable block lengths, and multiple code rates.