Duty cycle control apparatus |
| What is claimed is: 1. Apparatus for controlling the duty cycle of an input signal having a period, ... |
|
Signal level comparing circuit |
| It is accordingly an object of this invention to provide a signal level comparing circuit which can ... |
|
Circuit arrangement for correcting slip errors in pcm receivers |
| I claim: 1. In a receiver for binary code words including information bits and redundancy bits to ... |
|
Redundant clock system utilizing nonsynchronous oscillators |
| In accordance with the present invention, there is provided a clock system with two nonsynchronized ... |
|
|
Unit switching apparatus with failure detection
| Details |
Inventors: Soga, Kenji;
Assignee: NEC Corporation (Tokyo, JP)
Primary Examiner: Horabik; Michael
Assistant Examiner: Wilson, Jr.; William H.
Attorney, Agent or Firm: Foley & Lardner
A unit switching apparatus includes first and second current units, a spare unit, and a switching unit. Each of the current units includes a communication circuit for performing communication in accordance with set operation mode data and a failure detection circuit for detecting and notifying occurrence of a failure in the communication circuit. The spare unit includes a communication circuit for performing communication in accordance with set operation mode data, a memory for separately storing the operation mode data set in the communication circuits of the current units, and a CPU for, when the occurrence of the failure is notified by the failure detection circuit, reading out the operation mode data corresponding to the faulty current unit from the memory, and setting the data in the communication circuit. The switching unit switches the faulty current unit to the spare unit when the occurrence of the failure is notified by the failure detection circuit. |
|
DETAILED DESCRIPTION It is an object of the present invention to provide a unit switching apparatus which can set a spare unit with the same setting as that of a faulty current unit within a short period of time. In order to achieve the above object, according to the present invention, there is provided a unit switching apparatus comprising a plurality of first communication units of a current system, each of the first communication units including first communication means for performing communication in accordance with a set operation mode data and failure detection means for detecting and notifying an occurrence of a failure in the first communication means, a second communication unit of a spare system including second communication means for performing communication in accordance with a set operation mode data, storage means for separately storing the set operation mode data of the first communication means of the first communication units, and setting control means for, when the occurrence of the failure is notified by the failure detection means, reading out the set operation mode data corresponding to the faulty first communication unit from the storage means, and setting the set operation mode data in the second communication means, and unit switching means for switching the faulty first communication unit to the second communication unit when the occurrence of the failure is notified by the failure detection means.
|
| Related patents |
|
|
Dynamic random access memory device having sense amplifier circuit arrays sequentially activated
It is therefore an important object of the present invention to provide a dynamic random access memory device which is improved in data access speed. To accomplish these ...
|
|
|
Integrated semiconductor memory with parallel test capability and redundancy method
We claim: 1. An integrated semiconductor memory, comprising: U block groups (GP.sub.u=1 . . . U) each having groups of M memory cells (MC) and word lines (WL), and means ...
|
|
|
Method and apparatus for testing a connection between digital processing modules, such as in digital printing
We claim: 1. A method of testing a connection between a first module and a second module, the first module and second module being intended to exchange digital ...
|
|
|
Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same
The invention may be implemented in a semiconductor memory integrated circuit by providing response circuitry at the ends of signal lines internal to the memory. E...
|
|
|
Integrated circuit memory with column voltage holding circuit
An object of the present invention is to make an integrated circuit memory comprising a circuit that can be used to obtain a voltage at the column BL selected for the ...
|
|
|
Double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy, particularly for flash EEPROM devices
In view of the state of art described, the object of the present invention is to realize a row address decoding and selection circuitry which allows the simultaneous ...
|
|
|
Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
I claim: 1. A method of testing memory having a set of M memory locations, said method comprising the steps of: (a) generating a first sequence F.sub.k that is ...
|
|
|
Standby current detecting circuit for use in a semiconductor memory device and method thereof
Therefore, it is an object of the present invention to provide a standby current detecting circuit and method for detecting where within a semiconductor memory device a ...
|
|
|
Process and device for checking substrate wafers
Since a defect counting process, particularly a counting process carried out by an operator, is extremely time-consuming and tiring, one of the objects of the present ...
|
|
|
Synchro-to-digital converter
Accordingly, a primary object of the present invention is to provide a synchro-to-digital converter whereby digital values representing an absolute angular position of ...
|
|
|