 Monolithically integrated semiconductor store |
| An object of the invention is to further reduce the storage space required for a semiconductor ... |
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| Adaptive digital radio communication system |
| An illustrative embodiment of the adaptive digital radio communications system according to the ... |
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| Programmable, reconfigurable DSP implementation of a Reed-Solomon encoder/decoder |
| This invention relates to programmable, reconfigurable implementations of Reed-Solomon encoder/... |
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| Optimizing repeaters positioning along interconnects |
| A preferred embodiment of the present invention provides an aspect of interconnect design for ... |
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| Method and apparatus for placing repeaters in a network of an integrated circuit |
| OF THE PREFERRED EMBODIMENT(S) FIG. 1 is a schematic diagram of a network or net 100 that is used ... |
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| Parasitic element extraction apparatus |
| It is an object of the present invention to solve at least the problems in the conventional ... |
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| Bist architecture for measurement of integrated circuit delays |
| The IC to be tested is provided with, in one embodiment, a two-wire test bus, which passes near ... |
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Virtual multi-port RAM
| Details |
Inventors: Chappell, Barbara A.; Chappell, Terry I.; Ebcioglu, Mahmut K.; Schuster, Stanley E.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Clawson, Jr.; Joseph E.
Assistant Examiner:
Attorney, Agent or Firm: Whitham & Marhoefer
A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting. |
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DETAILED DESCRIPTION It is therefore an object of the present invention to provide a multi-port RAM structure which combines a multi-port function with the speed and density that cannot be matched with either conventional multi-port RAMs or multiple data copies in conventional single-port RAMs.
It is another object of the invention to provide a high-speed, high-density multi-port RAM wherein the order in which read and write operations are preformed is well defined, thus avoiding contention, and can be made programmable.
According to the invention, a virtual multi-port RAM (VMPRAM) is provided which employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple, self-timed on-chip cycles during one machine cycle.
The VMPRAM is implemented with the same array density and speed as a single-port RAM.
The virtual multi-port RAM structure is implemented in a preferred embodiment as a pipelined semiconductor memory chip segmented into a plurality of sub-arrays.
Each of the sub-arrays includes circuitry providing local self-timed reset and precharge functions independent of other sub-arrays.
The chip includes a plurality of address latches, a plurality of data-in latches and a plurality of data-out latches, each of the latches being sequentially interconnected to provide a set-up next cycle signal for enabling a succeeding latch.
Additional circuitry derives from a selected sub-array a release next cycle signal to said each of the plurality of address latches and the plurality of data-in latches to release next select signals and data to the sub-arrays thereby providing automatic port sequencing.
Also described is an architectural modification which provides for the port sequencing to be programmable while retaining the distinguishing VMPRAM feature of internal cycling derived from the self-timed cycling of the arrays.
The VMPRAM is especially important for practical realization of a recently proposed parallel computer architecture which achieves high performance with a very long instruction word (VLIW) and the use of parallel central processing units (CPUs) operating on the same instruction and/or data stream
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Fault Detection 
