High speed differential sense amplifier for use with single transistor memory cells
One embodiment of a memory array circuit constructed in accordance with the teachings of this invention is shown in the schematic diagram of FIG. 4. FIGS. 4a-4c define the schematic representations o... Read More
Inventors: Amin, Alaaeldin A. M.; Emoto, Bernard;, Assignee: National Semiconductor Corporation (Santa Clara, CA) |
Sense circuit for reading data stored in nonvolatile memory cells
There is a need for a sense circuit which although possessing static operating characteristics comparable to the static operating characteristics of a current-offset type circuit or anyway having a wi... Read More
Inventors: Pascucci, Luigi; Olivo, Marco;, Assignee: SGS-Thomson Microelectronics s.r.l. (IT) |
Fault tolerant system employing majority voting
An object of the present invention is to provide a fault tolerant system which is able to select and output a normal signal whenever there is at least one normal subsystem. Definition of Terms The def... Read More
Inventors: Kanekawa, Nobuyasu; Ihara, Hirokazu; Kato, Hatsuhiko;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
High speed bus with virtual memory data transfer capability using virtual address/data lines
An improved high speed bus with virtual memory capability is disclosed. The bus has particular application in computer systems which employ peripheral devices. The bus allows high speed data transfer ... Read More
Inventors: Bechtolsheim, Andreas;, Assignee: Sun Microsystems, Inc. (Mountain View, CA) |
Synchronizing two processors as an integral part of fault detection
What is claimed is: 1. A central processor unit including a fault detector means for detecting a fault in said central processor unit, said central processor unit comprising: a master processor means ... Read More
Inventors: McDonald, Keith M.;, Assignee: AG Communication Systems Corporation (Phoenix, AZ) |
Byzantine resilient fault tolerant shared memory data processing system
What is claimed is: 1. A fault tolerant data processing system for providing single fault Byzantine resilience, said system comprising: a plurality of fault containment regions each region including a... Read More
Inventors: Butler, Bryan P.; Harper, Richard E.;, Assignee: Charles Stark Draper Laboratory, Inc. (Cambridge, MA) |
Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems
It is the object of the current invention to provide a multiprocessor programmable interrupt controller (MPIC) system including, but not limited to, the following capabilities: 1) a means for properly... Read More
Inventors: Sarangdhar, Nitin V.; Papworth, Dave; Nizar, P. K.; Carson, David G.;, Assignee: Intel Corporation (Santa Clara, CA) |
Protocol for interrupt bus arbitration in a multi-processor system
One object of the present invention is to provide for a multi-processor programmable interrupt controller (MPIC) system that uses an integrated circuit chip incorporating both the local processor and ... Read More
Inventors: Nizar, P. K.; Carson, David;, Assignee: Intel Corporation (Santa Clara, CA) |
Multiprocessor computer backlane bus
OF THE PREFERRED EMBODIMENTS The following detailed description describes the logical, electrical, and connector specifications of Pyramid Technology Corporation's R-B us. The R-Bus is a proprietary ... Read More
Inventors: Myers, Mark; Lloyd, Stacey; Stout, Richard; Takasumi, Robert; Lynch, John;, Assignee: Pyramid Technology Corporation (San Jose, CA) |
Digital data processing methods and apparatus for fault detection and fault tolerance
The invention provides, in one aspect, a digital data processing device that includes a bus for transmitting signals (e.g., data and/or address information) between plural functional units (e.g., a ce... Read More
Inventors: Horvath, Charles J.; Leavitt, William I.; Tetreault, Mark D.; Green, Gregory M.; Churchill, Peter C.;, Assignee: Stratus Computer, Inc. (Marlboro, MA) |
Method and apparatus for allocating display memory and main memory employing access request arbitration and buffer control
The present invention, generally speaking, provides a low-cost, moderate performance small computer system by allowing a single sharable block of memory to be independently accessible as graphics or m... Read More
Inventors: Wu, Shih-Ho; Rhoden, William Desi; Nakahara, Mike;, Assignee: VLSI Technology, Inc. (San Jose, CA) |
Register set reordering for a graphics processor based upon the type of primitive to be rendered
The present invention provides a technique and protocol for reordering the register sets comprising the register file based upon the type of primitive to be rendered. Thus, the present invention elimi... Read More
Inventors: Larson, Michael Kerry; Harkin, Patrick A.;, Assignee: S3 Incorporated (Santa Clara, CA) |
Preamplification method and apparatus for dram sense amplifiers
An object of the present invention is to improve reliability of read out in DRAM. Another object of the present invention is to increase the potential difference applied to a sense amplifier of a DRAM... Read More
Inventors: Furutani, Kiyohiro; Arimoto, Kazutami;, Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP) |
Semiconductor memory device
It is an object of the present invention to provide a semiconductor memory device including a FAMOS transistor type redundancy decoder circuit suitable for practical use. The above object is attained ... Read More
Inventors: Higuchi, Mitsuo; Hagihara, Ryoji;, Assignee: Fujitsu Limited (Kawasaki, JP) |
Semiconductor device
It is accordingly the object of this invention to provide a reliable semiconductor device which enables binary data to be stored in a nonvolatile memory element without conducting current therethrough... Read More
Inventors: Iwahashi, Hiroshi; Ochii, Kiyofumi;, Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Kawasaki, JP) |
Data stream smoothing using a FIFO memory
The present invention is directed to the use of a FIFO memory for communicating data from a DRAM to a testing device in a continuous data stream despite interruptions for refresh cycles or long memory... Read More
Inventors: Graeve, Egbert;, Assignee: Schlumberger Tecnologies, Inc. (San Jose, CA) |
Semiconductor memory device having redundant circuit
Accordingly, a first object of this invention is to provide a semiconductor memory device capable of enhancing the access speed. A second object of this invention is to provide a semiconductor memory ... Read More
Inventors: Takeuchi, Hideki; Hayakawa, Shigeyuki; Yabe, Tomoaki;, Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP) |
Redundant address decoder
Accordingly, an object of the present invention is to provide a redundant address decoder which can improve the memory access speed by providing a sufficient increase in potential for a redundant word... Read More
Inventors: Shibata, Kenji; Kodama, Yukinori;, Assignee: Fujitsu Limited (Kawasaki, JP) |
Automatic transition charge pump for nonvolatile memories
Generally, the present invention provides a high voltage charge pump for programming a non-voltage memory that can operate at more than one power supply voltage. A low voltage detector is used to aut... Read More
Inventors: Dinh, Khoi Van;, Assignee: Motorola, Inc. (Schaumburg, IL) |
High speed static BiCMOS memory with dual read ports
A memory includes a plurality of cells with each cell containing a pair of cross-coupled N-channel field-effect transistors having set and reset nodes. Also in each cell, a first P-channel transistor ... Read More
Inventors: Shookhtim, Rimon; Lee, Lo-Shan; Mansoorian, Babak;, Assignee: Unisys Corporation (Blue Bell, PA) |
Flexible redundancy architecture and fuse download scheme
What is claimed is: 1. In an integrated circuit comprising a plurality of circuit elements, some of which may be faulty, which respond to a discrete set of access signals, and a plurality of redundant... Read More
Inventors: Hiltebeitel, Nathan R.; Pontius, Dale E.; Tomashot, Steven W.;, Assignee: International Business Machines Corporation (Armonk, NY) |
Flexibilitiy for column redundancy in a divided array architecture
The present invention relates to an apparatus and method for implementing flexible redundancy memory blocks in a divided array architecture scheme incorporating a plurality of memory sub-arrays, and m... Read More
Inventors: Phelan, Cathal G.;, Assignee: Cypress Semiconductor Corporation (San Jose, CA) |
Row redundancy block architecture
It is therefore an object of the present invention to provide a redundancy block architecture which uses a row redundancy control circuit arrangement that effectively reduces design space. It is a fur... Read More
Inventors: DeBrosse, John; Kirihata, Toshiaki; Wong, Hing;, Assignee: International Business Machines Corporation (Armonk, NY) |
Partitioned dynamic memory allowing substitution of a redundant circuit in any partition and using partial address disablement and disablement override
It is therefore an object of the present invention to provide a circuit architecture applicable, for example, to a DRAM memory and which is partitioned for parallel, concurrent refresh of all partitio... Read More
Inventors: Beiley, Mark Adam; Drake, Charles Edward; Obremski, Thomas Edward;, Assignee: International Business Machines Corporation (Armonk, NY) |
Shortened timeout period during frame retry in a communication link
The present invention is embodied in a system and method for asynchronously transmitting data blocks between two information handling systems. Two carriers are used to interconnect two systems and to ... Read More
Inventors: Gregg, Thomas A.; Hoke, Joseph M.; Ing, Albert; Lee, Chin;, Assignee: International Business Machines Corporation (Armonk, NY) |
System for selectively reducing capture effect in a network station by increasing delay time after a predetermined number of consecutive successful transmissions
We claim: 1. In a network station coupled to media of a network, a method of accessing the media, comprising: determining if a number of consecutive successful transmissions by the network station exc... Read More
Inventors: Krishna, Gopal; Kalkunte, Mohan;, Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Media access control receiver and network management system
Broadly speaking, the present invention fills these needs by providing methods and apparatuses for a high speed media access controller used to process packet data and control information in an in-lin... Read More
Inventors: Sambamurthy, Namakkal S.; Tripathi, Devendra K.; Deb, Alak K.; Truong, Linh Tien; Kumar, Praveen D.;, Assignee: XAQTI Corporation (Santa Clara, CA) |
System and method of printer image warping
The present invention is directed to apparatus and method for aligning a print image to be printed by a printer to a desired position. One method of the invention includes the steps of: determining a ... Read More
Inventors: Bender, Michael Donald; Johnson, Allen Patrick; Sherwood, Gregory John; Yoder, Aaron Charles;, Assignee: Lexmark International, Inc. (Lexington, KY) |
Initialization system for input/output processing units
It is therefore an object of the present invention to acquire correct failure information by positively initializing an input/output processing unit after the acquisition of failure information. A fea... Read More
Inventors: Fujioka, Shuntaro;, Assignee: Fujitsu Limited (Kawasaki, JP) |
Communication system capable of detecting missed messages
An object of the present invention is to provide a communication system of high reliability requiring no complex control so that overhead of processing can be decreased. According to this invention, i... Read More
Inventors: Seki, Toshibumi;, Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP) |
Fault Detection 
