Logic for calculating bit error rate in a data communication system
I claim: 1. In a communication system for transmitting and receiving a high speed stream of data bits, a method of determining the current bit error rate but not the specific bits that are in error an... Read More
Inventors: Schiff, Leonard N.;, Assignee: RCA Corporation (Princeton, NJ) |
Multiprocessor system formed by microprocessor matrix
We claim: 1. A multiprocessor system comprising a matrix of 32 standard microcomputer modules, connected for microprocessor exchange by an interconnection network of communication nodes with cyclic st... Read More
Inventors: Borovski, Boris H.; Ilieva, Plamenka I.;, Assignee: Vmei "Lenin" (Sofia, BG) |
Transmission system using forward error correction
What is claimed is: 1. A method of processing information including fixed positive stuffed information, comprising the step of replacing at least some fixed positive stuffed information with error con... Read More
Inventors: Grover, Wayne D.;, Assignee: Northern Telecom Limited (Montreal, CA) |
Digital satellite exchange
The invention consists in a digital satellite exchange for connecting analog and digital subscriber lines, comprising a digital connecting and control unit, a plurality of subscriber line digital conc... Read More
Inventors: kaczerowski, Andre;, Assignee: Compagnie Industrielle des Telecommunications Cit-Alcatel (Paris, FR) |
Data transmission apparatus
The present invention is directed to the provision of an approach to solve the aforementioned problem encountered in the prior art data transmission apparatus. According to one embodiment of the inven... Read More
Inventors: Yoshioka, Kazuo;, Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP) |
Mobile radio-receiver system with improved reproduction characteristics of reception signal having noise superimposed thereon
An object of the present invention is to provide an improved and novel mobile radio-receiver system which can effectively eliminate an affect of noise superimposed on a received signal and applied to ... Read More
Inventors: Takayama, Kazuo; Fuse, Hidefumi;, Assignee: Fujitsu Ten Limited (Hyogo, JP); Toyota Jidosha Kabushiki Kaisha (Aichi, JP) |
Electronic robot key distributor
Apparatus for storing and dispensing articles comprises a cylindrically arranged array of a plurality of storage compartments, each of which has an exterior opening at the cylindrical surface. An encl... Read More
Inventors: Pelletier, Florent; Coulombe, Lionel;, Assignee: |
Apparatus and method for multistage electrical signal processing
The present invention provides multistage electrical signal processing apparatus comprising a plurality of signal processing elements distributed across a plurality of devices interconnected to form a... Read More
Inventors: Yassaie, Mohamad H.; King-Smith, Anthony D.; Dyson, Clive M.;, Assignee: INMOS Ltd. (Bristol, GB2) |
Geometric processing system
It is therefore an object of the present invention to provide a geometric processing system which is capable of locally processing geometric or graphic data so as to achieve an efficient data processi... Read More
Inventors: Ohsawa, Akira;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Address multiplexed dynamic RAM having a test mode capability
It is an object of the present invention to provide a method wherein a dynamic RAM device which can be tested in a shorter period of time without having an increased number of external terminals. The ... Read More
Inventors: Miyazawa, Kazuyuki; Shimohigashi, Katsuhiro; Etoh, Jun; Kimura, Katsutaka;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test
A main object of the present invention is to provide a semiconductor memory device including a test circuit which can shorten a time required for a disturb refresh test. Another object of the present ... Read More
Inventors: Tanida, Susumu; Hirayama, Kazutoshi; Suzuki, Tomio; Hayashikoshi, Masanori;, Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP) |
Display device of the galvanometric or logometric type, including a control circuit in form of an integrated circuit chip
I claim: 1. A display device with a winding a pivoting element of the galvanometic or logometric type, comprising: a case, a support of electrically insulating material fixed with said case, at least ... Read More
Inventors: Chapotot, Michel;, Assignee: Jaeger (Lavallois Perret, FR) |
Hierarchical redundancy scheme for high density monolithic memories
OF THE INVENTION FIG. 2 shows a block diagram of a monolithic high density memory device 30 that utilizes a hierarchical redundancy scheme in accordance with the present invention. The memory 30 is s... Read More
Inventors: Reddy, Chitranjan N.; Medhekar, Ajit K.;, Assignee: Alliance Semiconductor Corporation (San Jose, CA) |
Static memory long write test
It would be advantageous in the art to employ a long write testing method which effectively and efficiently tests memory cells of a static memory for leakage problems using minimal control circuitry. ... Read More
Inventors: McClure, David C.;, Assignee: SGS-Thomson Microelectronics, Inc. (Carrollton, TX) |
Semiconductor memory device
OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment of the semiconductor memory device according to the present invention, in which the sense amplifiers of differential amplifier circuits ar... Read More
Inventors: Muraoka, Kazuyoshi; Koyanagi, Masaru; Takeuchi, Yoshiaki;, Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP) |
Modem use monitor
What is claimed is: 1. A device for analyzing modem defects among a plurality of modems formed into one or more groups thereof, each said group of modems sequentially serving a rotary hunt arrangement... Read More
Inventors: Kelly, Robert J.; Kelly, Tadhg;, Assignee: |
Test circuit in clock synchronous semiconductor memory device
An object of the present invention is to provide an SDRAM which can efficiently make a test. Another object of the present invention is to provide a semiconductor memory device which can efficiently m... Read More
Inventors: Sawada, Seiji; Konishi, Yasuhiro;, Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP) |
Semiconductor memory device
Accordingly, it is an object of the present invention to provide a semiconductor memory device capable of selecting both fast and slow operations and suppressing current consumption in a slow operatio... Read More
Inventors: Kanma, Hirokazu; Takenouchi, Akira; Tanaka, Masahiro;, Assignee: Fujitsu Limited (Kawasaki, JP) |
Majority circuit, a controller and a majority LSI
OF THE PREFERRED EMBODIMENTS Embodiment 1. FIG. 1 is a block diagram which shows a general configuration of the majority circuit related to Embodiment 1 of the invention. For clarity sake, the same s... Read More
Inventors: Tanabe, Takashi; Kamemaru, Toshihisa; Katoh, Mamoru; Ohno, Tsugihiko; Hatashita, Toyohito; Abe, Kaoru;, Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP) |
Semiconductor memory device
Therefore, an object of the present invention is to provide a semiconductor memory device in which a vendor test is performed by using fuse ROMs which are programmed by external signals so that based ... Read More
Inventors: Joo, Yang S.;, Assignee: LG Semicon Co., Ltd. (Choongchungbook-do, KR) |
Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell
The invention is an integrated circuit operable in a test mode and a normal operating mode, which includes an improved test mode switch. In preferred embodiments, the integrated circuit is an integrat... Read More
Inventors: Roohparvar, Fariborz F.; Briner, Michael S.;, Assignee: Micron Technology, Inc. (Santa Clara, CA) |
Apparatus for testing signal timing and programming delay
According to the present invention, method and apparatus are provided for adjusting on-chip timed pulses enabling the fast, efficient nonpermanent testing and retesting of semiconductor memories at va... Read More
Inventors: McClure, David Charles;, Assignee: STMicroelectronics, Inc. (Carrollton, TX) |
Robust delay fault built-in self-testing method and apparatus
Briefly described, the present invention comprises a method and apparatus for robust delay-fault testing of an integrated circuit (IC) by altering the circuit topology. Hazardous nodes are determined ... Read More
Inventors: Bushnell, Michael L.; Shaik, Imtiaz;, Assignee: Rutgers University (Piscataway, NJ) |
Concurrent row/column syndrome generator for a product code
An efficient error correction processor is disclosed for correcting a multi-dimensional code comprising a first set of codewords that intersect with a second set of codewords. The error correction is ... Read More
Inventors: Zook, Christopher P.; Kato, Keisuke; Au, Frederick Siu-Huang; Yoon, Tony Jihyun;, Assignee: Cirrus Logic, Inc. (Fremont, CA) |
Preprogramming testing in a field programmable gate array
Thus the present invention provides for an integrated circuit which has a plurality of terminals for providing electrical paths to and from said integrated circuit. The integrated circuit also has an ... Read More
Inventors: Cooke, Laurence H.; Phillips, Christopher E.; Allen, William J.;, Assignee: Crosspoint Solutions Inc. (Santa Clara, CA) |
Method and hardware arrangement for replacing defective function blocks in an integrated circuit
It is an object of the present invention to provide improved defective block replacement techniques by which the yield of chips can effectively be raised without a complex block connector. In brief, t... Read More
Inventors: Kimura, Tohru;, Assignee: NEC Corporation (Tokyo, JP) |
Multiple clock rate test apparatus for testing digital systems
We claim: 1. A method for testing a digital system comprising a plurality of scannable memory elements and at least one combinational network, the method comprising: configuring the memory elements in... Read More
Inventors: Nadeau-Dostie, Benoit; Hassan, Abu S. M.; Burek, Dwayne M.; Sunter, Stephen K.;, Assignee: Northern Telecom Limited (Montreal, CA) |
Method and apparatus for parallel testing of memory circuits
In accordance with the present invention, a method and apparatus for testing memories is provided which substantially eliminates the disadvantages associated with prior memory testing devices. In the ... Read More
Inventors: Hashimoto, Masashi;, Assignee: Texas Instruments Incorporated (Dallas, TX) |
Logic performance verification and transition fault detection
What is claimed is: 1. In a scan test system operated in a plurality of machine cycles to test a logic network, the test system comprising a first means having a first portion for receiving test data ... Read More
Inventors: Corr, James L.; Vincent, Brian J.;, Assignee: International Business Machines Corporation (Armonk, NY) |
Serial and parallel scan technique for improved testing of systolic arrays
OF THE PREFERRED EMBODIMENT Indicated generally at 10 is a circuit constructed in accordance with the present invention. Circuit 10 is sometimes referred to as a systolic array. In the present embodi... Read More
Inventors: Anderson, Daryl E.; Lanham, Ralph H.; Jaarsma, Neal C.;, Assignee: Hewlett-Packard Company (Palo Alto, CA) |
Fault Detection 
