Music synthesizer
What I claim is: 1. In a music synthesis apparatus having associated music signal utilization means, the improvement comprising in combination, a. a source of variable control voltage, b. at least one... Read More
Inventors: Faulhaber, Mark Edwin;, Assignee: |
Method and apparatus for arbitrating conflicts by monitoring number of access requests per unit of time in multiport memory systems
What we claim is: 1. A method for arbitrating conflicting memory transfer requests in a multiport memory system including first and second memory ports, said method comprising the steps of: monitoring... Read More
Inventors: Kalkunte, Ramsesh; Rege, Satish; Edgar, Ronald;, Assignee: Digital Equipment Corporation (Maynard, MA) |
Semiconductor memory device having flip-flop circuits
In order to solve the above explained problems of prior art semiconductor memory devices having flip-flop circuits, the present invention has as an object the provision of a dummy line which is arrang... Read More
Inventors: Nakano, Masao; Nakano, Tomio; Takemae, Yoshihiro; Kabashima, Katsuhiko;, Assignee: Fujitsu Limited (JP) |
Self-isolating cross-coupled sense amplifier latch circuit
It is accordingly an object of the present invention to provide an improved sense amplifier latching circuit using field effect transistors of both the enhancement and depletion mode. It is another ob... Read More
Inventors: Freeman, Leo Boyes; Incerto, Robert James; Petrosky, Jr., Joseph Anthony;, Assignee: International Business Machines Corporation (Armonk, NY) |
Cassette with removable disc
Part of the housing is constituted by a door or end closure which is movable relative to the remainder of the housing between an open and a closed position, the door including at least a portion of on... Read More
Inventors: Ouwerkerk, Cornelius; Beijersbergen Van Henegouwen, Cornelis M.; Rath, Wilhelmus J. F.; Koken, Karel G. M.;, Assignee: U.S. Philips Corporation (New York, NY) |
Optical detection and logic devices with latching function
It is object of the invention to provide improved apparatus and methods of optical detection and logic devices with latching functions optical logic devices and methods. According to the present inven... Read More
Inventors: Roberts, Kim Byron;, Assignee: Northern Telecom Limited (Montreal, CA) |
Optical-fibre passively mode locked laser generator with non-linear polarization switching
The present invention concerns an active-fibre laser that is passively-mode-locked and particularly suited for emission of solitons. In an aspect the present invention concerns an active-fibre passive... Read More
Inventors: Fontana, Flavio;, Assignee: Pirelli Cavi S.p.A. (Milan, IT) |
Connection set-up and path assignment in wavelength division multiplexed ring networks
These shortcomings and other limitations and deficiencies are obviated in accordance with the present invention by a wavelength assignment and routing approach that is systematic, can handle either an... Read More
Inventors: Ellinas, Georgios Nicos; Bala, Krishna; Chang, Gee-Kung;, Assignee: Telcordia Technologies, Inc. (Morristown, NJ) |
Magnetic printing machine employing a multi-channel recording head with minimal cross-talk with secondary scanning head movement
An object of this invention is to provide a magnetic printing machine in which there is no cross talk, and which has high resolving power. Another object of this invention is to provide a magnetic pri... Read More
Inventors: Kokaji, Norio;, Assignee: Iwatsu Electric Co., Ltd. (Tokyo, JP) |
Phase-lock loop circuit with fuzzy control
These and other objects and advantages are achieved by providing a phase-lock circuit with fuzzy logic control, which includes a phase comparator whose output is connected to a low-pass filter, said l... Read More
Inventors: Travaglia, Federico; La Rosa, Maria Grazia; Giarrizzo, Guido;, Assignee: SGS-Thomsom Microelectronics S.r.l. (Agrate Brianza, IT); Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno (Catania, IT) |
Programmable variable length high speed digital delay line
What is claimed is: 1. A variable length, high speed, digital delay line apparatus comprising in combination: a set of serially arranged, fixed-length, digital delay units, and a set of switching unit... Read More
Inventors: Ramsey, John L.; Post, Allen E.;, Assignee: The United States of America as represented by the Secretary of the Air (Washington, DC) |
Bus station abort detection
An abort detection circuit for inclusion in each operational component of a multi-component system in which these components are interconnected through a bus that is under the control of a controller ... Read More
Inventors: Byers, Larry L.; Desubijana, Joseba M.; Michaelson, Wayne A.;, Assignee: Unisys Corporation (Blue Bell, PA) |
Asynchronous anticontention logic for bi-directional signals
The present invention concerns an asynchronous anticontention circuit for a bi-directional bus. The asynchronous anticontention circuit comprises an anticontention circuit coupled to an asynchronous d... Read More
Inventors: Choy, Garrett; Graf, III, W. Alfred;, Assignee: Cypress Semiconductor Corp. (San Jose, CA) |
Method of handshaking in a data communications bus
OF THE DRAWINGS Throughout this description, the preferred embodiment and examples shown should be considered as exemplars, rather than limitations on the apparatus and methods of the present inventi... Read More
Inventors: Bemanian, Majid; Bailey, John;, Assignee: Timeplex, Inc. (Woodcliff Lake, NJ) |
Apparatus for recognition of approximate shape of an article
What is claimed is: 1. A method for the recognition of the approximate shape of an article, which comprises finding from the projection of said article the largest width, the largest height and the ar... Read More
Inventors: Kono, Hidehiko; Oka, Masayo; Kawamura, Sadakazu;, Assignee: Agency of Industrial Science & Technology (Tokyo, JA); Ikegami Tsushinki Co., Ltd. (Tokyo, JA); Hitachi Denshi Kabushiki Kaisha (Tokyo, JA) |
Clock generating circuit for use in single chip microcomputer
Accordingly, it is an object of the present invention to provide a basic clock signal generating circuit which has overcome the above mentioned defect of the conventional one. Another object of the pr... Read More
Inventors: Akiyama, Shin-ichiro;, Assignee: NEC Corporation (Tokyo, JP) |
Method and apparatus for power management of an integrated circuit
Embodiments of the present invention include a clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present i... Read More
Inventors: Wong, Keng L.; Fitzpatrick, Kelly J.; Smith, Jeffrey E.;, Assignee: Intel Corporation (Santa Clara, CA) |
Adaptive expansion bus
The following sets forth a detailed description of the best contemplated mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken t... Read More
Inventors: Miller, Kevin L.; Pecone, Victor K.;, Assignee: Dell USA, L.P. (Round Rock, TX) |
Apparatus and method for synchronously providing a fullness indication of a dual ported buffer situated between two asynchronous buses
OF THE PREFERRED EMBODIMENT Referring to FIG. 1, there is illustrated a computer system C utilizing the preferred embodiment of the present invention. A central processing unit (CPU) 104 is coupled t... Read More
Inventors: Callison, Ryan A.; Chandler, Gregory T.;, Assignee: Compaq Computer Corporation (Houston, TX) |
Apparatus and method of layering cache and architectural specific functions to permit generic interface definition
It is therefore one object of the present invention to provide an improved cache controller for a data processing system. It is another object of the present invention to provide an improved cache con... Read More
Inventors: Arimilli, Ravi Kumar; Dodson, John Steven; Lewis, Jerry Don; Williams, Derek Edward;, Assignee: International Business Machines Corporation (Armonk, NY) |
Transparent bridge between of a computer system and a method of interfacing the buses to operate as a single logical bus
There is a need for a bridge which provides electrical isolation between buses to comply with bus specifications, but allows two connected buses to be viewed from the software as a single logical bus.... Read More
Inventors: Kenny, John D.; Shah, Pranay D.;, Assignee: National Semiconductor Corporation (Santa Clara, CA) |
Interactive terminal system using a prepoll prior to transferring information from the controller to the work station
An interactive terminal data processing system includes a high speed link controller (HSLC) and a number of work stations, all coupled in common to a single conductor coaxial bus. Information is trans... Read More
Inventors: Kelley, Jr., George E.; Peisel, William E.; Goldberg, Edward H.;, Assignee: Honeywell Information Systems Inc. (Waltham, MA) |
Information transmission and reception system for a vehicle
With these various problems in mind, it is an object of the present invention to provide a transmission and reception system for a vehicle with a simple structure and with no need for a high-level pro... Read More
Inventors: Futami, Toru; Suzuki, Tadashi; Sakagami, Atsushi;, Assignee: Nissan Motor Company, Ltd. (JP) |
Method and system for monitoring fieldbus network with dynamically alterable packet filter
OF THE DRAWINGS Turning now to the drawings, FIG. 1 is a block diagram of fieldbus network 10. System 10 is comprised of a fieldbus 16 and a plurality of fieldbus devices 12 connected to fieldbus 16.... Read More
Inventors: Gretta, Jr., Robert E.;, Assignee: National Instruments Corporation (Austin, TX) |
Switching system reliability
The description which follows relates to call processing in a distributed switching system in accordance with two call processing modes-a first mode where paths are selected without reference to whet... Read More
Inventors: Ardon, Menachem T.;, Assignee: AT&T Bell Laboratories (Murray Hill, NJ) |
Network and intelligent cell for providing sensing, bidirectional communications and control
A network for providing sensing, communications and control is described. A plurality of intelligent cells each of which comprises an integrated circuit having a processor and input/output section are... Read More
Inventors: Markkula, Jr., Armas C.; Sander, Wendell B.; Evan, Shabtai; Smith, Stephen B.; Twitty, William B.;, Assignee: Echelon Corporation (Palo Alto, CA) |
ATM exchanger
What is claimed is: 1. An ATM exchanger for executing statistical multiplex transmission of digitized multimedia data from data terminals connected to a private branch exchange (PBX) over an ATM netwo... Read More
Inventors: Shimokasa, Kiyoshi;, Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP) |
Method for rejecting cells at an overloaded node buffer
The objective of the invention is to eliminate the above-mentioned problems. The purpose of the present invention is especially to achieve a novel method and system in order to control a buffer, i.e. ... Read More
Inventors: Heinanen, Juha; Kilkki, Kalevi;, Assignee: Sonera OY (Helsinki, FI) |
Non-buffered, non-blocking multistage ATM switch
What is claimed is: 1. A multi stage asynchronous transfer mode switch system comprising: switch elements with inputs switchable to outputs, said switch elements defining a matrix with an input stage,... Read More
Inventors: Koning, G. Paul; Ramelson, Brian;, Assignee: 3Com Corporation (Santa Clara, CA) |
Packet data communications system having a malfunction list
FIG. 1 shows one example of a packet communication network. In FIG. 1, the packet communication network 100 has a circuit configuration such that packet switching nodes 102 are mutually connected by ... Read More
Inventors: Lindqvist, Pontus; Andersson, Ingvar Gustaf; Henriksson, Anders; Andersson, Per Erik;, Assignee: Telefonaktiebolaget LM Ericsson (Stockholm, SE) |
Fault Detection 
