Mixing and modulating methods and structures using nonlinear optical amplifiers
The present invention is directed to mixing and modulating methods and structures which can generate intermodulation products of radio-frequency signals on an optical carrier without the penalty of an... Read More
Inventors: Lam, Juan F.; Stephens, Ronald R.; Tangonan, Gregory L.;, Assignee: Hughes Electronics Corporation (El Segundo, CA) |
Active receiving antenna
It is the object of the present invention to provide a high-powered slot antenna arrangement with which different polarized waves are received and which can be easily adapted to a vehicle body. The ab... Read More
Inventors: Biebl, Erwin; Luy, Johann-Friedrich;, Assignee: Daimler-Benz Aktiengesellschaft (Stuttgart, DE) |
Input stage for a CTD low-pass filter
What is claimed is: 1. An input stage for a CTD low-pass filter, comprising a semiconductor substrate, an insulating layer deposited upon the substrate, said substrate comprising at least two insulate... Read More
Inventors: Benoit-Gonin, Roger; Berger, Jean L.; Fontanes, Sylvain;, Assignee: Thomson-CSF (Paris, FR) |
Photonic cross-connect switch
Lithium niobate switches permit rapid switching of optical signals without reconversion to electrical form. By diffusing strips of titanium into a LiNbO.sub.3 substrate, single mode waveguides with h... Read More
Inventors: Fatehi, Mohammad T.; Srinivasan, Nattu V.;, Assignee: AT&T Bell Laboratories (Murray Hill, NJ) |
Card keying device
A male-female keying device for uniquely pairing circuit cards and a connector. The keying code can be altered. An elongated pin at each end of the device acts as a guide for ease in assembling the ma... Read More
Inventors: Waite, Robert J.; Almeida, Ronald P.;, Assignee: Zero Corporation (Burbank, CA) |
Highspeed parallel adder with clocked switching circuits
It is an object of the present invention to provide full adder circuits which can constitute a parallel adder circuit arranged to shorten the carry propagation delay time. It is another object to prov... Read More
Inventors: Sahoda, Masayuki; Tanaka, Fuminari; Iida, Tetsuya;, Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP) |
Magneto-optical recording and reproducing apparatus having a magnetization direction detecting apparatus for a magnetic recording medium
What is claimed is: 1. A magneto-optical recording and reproducing apparatus having a direction of magnetization detecting apparatus of a magnetic recording medium, characterized in that a rectilineal... Read More
Inventors: Sato, Noboru; Watanabe, Kenjirou;, Assignee: Sony Corporation (Tokyo, JP) |
Electronic timepiece
OF THE PREFERRED EMBODIMENT The present invention will be described in the following in connection with the embodiment thereof with reference to the accompanying drawings. FIGS. 1 and 2 are block dia... Read More
Inventors: Inoue, Yuichi; Odagiri, Hiroshi; Masaki, Hiroyuki; Ohtawa, Shuji; Kasuga, Masao;, Assignee: Seiko Instruments Inc. (Tokyo, JP) |
System and method for monitoring point identification
OF THE PREFERRED EMBODIMENTS The present invention is directed to an improved system and method for enhancing the performance monitoring capabilities of a telecommunications network management system... Read More
Inventors: Brownmiller, Curtis; Bencheck, Michael; Tran, Minh T.; Branton, Robert; DeMoss, Mark; Landon, Steve;, Assignee: MCI Communications Corporation (Washington, DC) |
Unit switching apparatus with failure detection
It is an object of the present invention to provide a unit switching apparatus which can set a spare unit with the same setting as that of a faulty current unit within a short period of time. In order... Read More
Inventors: Soga, Kenji;, Assignee: NEC Corporation (Tokyo, JP) |
Dynamic random access memory device having sense amplifier circuit arrays sequentially activated
It is therefore an important object of the present invention to provide a dynamic random access memory device which is improved in data access speed. To accomplish these objects, the present invention... Read More
Inventors: Takada, Masahide;, Assignee: NEC Corporation (Tokyo, JP) |
Integrated semiconductor memory with parallel test capability and redundancy method
We claim: 1. An integrated semiconductor memory, comprising: U block groups (GP.sub.u=1 . . . U) each having groups of M memory cells (MC) and word lines (WL), and means for simultaneously testing sev... Read More
Inventors: Muhmenthaler, Peter; Oberle, Hans D.; Peisl, Martin; Savignac, Dominique;, Assignee: Siemens Aktiengesellschaft (Munich, DE) |
Method and apparatus for testing a connection between digital processing modules, such as in digital printing
We claim: 1. A method of testing a connection between a first module and a second module, the first module and second module being intended to exchange digital information over a plurality of parallel... Read More
Inventors: Baldwin, Steven W.; OuYang, William M.; York, James R.; Cheng, Wayne; McGarvey, Ronald E.; Perez, Ana M.; Creus, Carolina; Ulrich, Vernon W.;, Assignee: Xerox Corporation (Stamford, CT) |
Testing circuitry of internal peripheral blocks in a semiconductor memory device and method of testing the same
The invention may be implemented in a semiconductor memory integrated circuit by providing response circuitry at the ends of signal lines internal to the memory. Examples of such signal lines include ... Read More
Inventors: Slemmer, William C.;, Assignee: SGS-Thomson Microelectronics, Inc. (Carrollton, TX) |
Integrated circuit memory with column voltage holding circuit
An object of the present invention is to make an integrated circuit memory comprising a circuit that can be used to obtain a voltage at the column BL selected for the recording of a binary value that ... Read More
Inventors: Rouy, Olivier;, Assignee: SGS-Thomson Microelectronics S.A. (Saint Genis Pouilly, FR) |
Double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy, particularly for flash EEPROM devices
In view of the state of art described, the object of the present invention is to realize a row address decoding and selection circuitry which allows the simultaneous selection of two adjacent defectiv... Read More
Inventors: Golla, Carla M.; Olivo, Marco;, Assignee: SGS-Thomson Microelectronics S.r.l. (Agrate Brianza, IT) |
Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
I claim: 1. A method of testing memory having a set of M memory locations, said method comprising the steps of: (a) generating a first sequence F.sub.k that is pseudorandom; (b) generating a second se... Read More
Inventors: Zerbe, Jared L.;, Assignee: VLSI Technology, Inc. (San Jose, CA) |
Standby current detecting circuit for use in a semiconductor memory device and method thereof
Therefore, it is an object of the present invention to provide a standby current detecting circuit and method for detecting where within a semiconductor memory device a short circuit is generated. An ... Read More
Inventors: Han, Jin-Man; Yoo, Jei-Hwan;, Assignee: Samsung Electronics, Co., Ltd. (Suwon, KR) |
Process and device for checking substrate wafers
Since a defect counting process, particularly a counting process carried out by an operator, is extremely time-consuming and tiring, one of the objects of the present invention is to develop a process... Read More
Inventors: Schmidt, Walter;, Assignee: Swiss Aluminium Ltd. (Chippis, CH) |
Synchro-to-digital converter
Accordingly, a primary object of the present invention is to provide a synchro-to-digital converter whereby digital values representing an absolute angular position of the rotor of a synchro can be ob... Read More
Inventors: Aramaki, Shigeru;, Assignee: Tamagawa Seiki Kabushiki Kaisha (JA) |
Duty cycle control apparatus
What is claimed is: 1. Apparatus for controlling the duty cycle of an input signal having a period, said apparatus comprising: control means for controlling the amplitude of the input signal; means re... Read More
Inventors: Hall, George R.; Hall, Robert J.;, Assignee: Norlin Industries, Inc. (White Plains, NY) |
Signal level comparing circuit
It is accordingly an object of this invention to provide a signal level comparing circuit which can process an input signal whose maximum voltage level stands higher than the voltage of an operation p... Read More
Inventors: Matsuo, Kenji; Takata, Minoru;, Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Kawasaki, JP) |
Circuit arrangement for correcting slip errors in pcm receivers
I claim: 1. In a receiver for binary code words including information bits and redundancy bits to enable detection of an error, in combination: a line carrying incoming code words; a plurality of erro... Read More
Inventors: Valbonesi, Giuseppe;, Assignee: Societa Italiana Telecomunicazioni Siemens S.p.A. (Milan, IT) |
Redundant clock system utilizing nonsynchronous oscillators
In accordance with the present invention, there is provided a clock system with two nonsynchronized digital clocks, each having a select circuit for selecting the output signal of one of the clocks to... Read More
Inventors: McDermott, III, Thomas C.;, Assignee: Rockwell International Corporation (El Segundo, CA) |
Fault Detection 
