State metric memory arrangement for a viterbi decoder
In accomplishing the object of the present invention, a novel state metric memory apparatus is shown. In one embodiment, a state metric memory arrangement for a VITERBI decoder includes a register for... Read More
Inventors: Porter, Jeffrey A.;, Assignee: Motorola, Inc. (Schaumburg, IL) |
Decoding method for trellis codes with large free distances
This invention is a decoding method for the trellis code T of which the encoding can be implemented by first using the encoder of a binary convolutional code C.sup.(1) to map a message u(t) into v.sup... Read More
Inventors: Lin, Mao-Chao; Wang, Jia-Yin;, Assignee: Chen; Chung-Chin (Alexandria, VA) |
Methods, apparatus and systems for real time identification and control modes of oscillation
The present invention provides a novel approach for active control of detrimental instabilities in practical combustors or the excitation of beneficial acoustic oscillations in combustion and energy i... Read More
Inventors: Neumeier, Yedidia; Zinn, Ben T.;, Assignee: Georgia Tech Research Corporation (Atlanta, GA) |
System for turbo-coded satellite digital audio broadcasting
It is an object of the present invention to provide an improved DAB method and system using an implementation of turbo code over two complementary satellite links in the DAB system to allow the reduct... Read More
Inventors: Yi, Byung Kwan;, Assignee: Orbital Sciences Corporation (Dulles, VA) |
Communications system handoff operation combining turbo coding and soft handoff techniques
What is claimed is: 1. A mobile communication system, comprising: a source of digital data, for communication to or from a predetermined one of a plurality of mobile stations; a first constituent enco... Read More
Inventors: Yi, Byung Kwan;, Assignee: Orbital Sciences Corporation (Dulles, VA) |
System for coding system
OF THE PREFERRED EMBODIMENT Having summarized the present invention, reference will now be made in detail to the description of the invention as illustrated in the drawings. While the invention will ... Read More
Inventors: Herzberg, Hanan;, Assignee: |
Process for transmitting information bits with error correction coding, coder and decoder for the implementation of this process
The invention therefore proposes, in a process of the type indicated in the introduction, that a set of Y bits respectively having Y determined positions in the second binary matrix should not be tran... Read More
Inventors: Pyndiah, Ramesh; Adde, Patrick;, Assignee: France Telecom (Paris, FR) |
Process for transmitting information bits with error correction coding and decoder for the implementation of this process
The invention therefore proposes in a process of the type indicated in the introduction, that the first binary matrix comprises, in addition to the information bits, a set of bits with values a priori... Read More
Inventors: Pyndiah, Ramesh; Adde, Patrick;, Assignee: France Telecom (Paris, FR) |
Punctured serial concatenated convolutional coding system and method for low-earth-orbit satellite data communication
In accordance with this invention, a coding system ideally suited for use in a low-Earth-orbit (LEO) satellite data communication network is provided. Data to be transmitted from one location on the e... Read More
Inventors: Hinedi, Sami M.; Griep, Karl R.; Million, Samson;, Assignee: Teledesic LLC (Kirkland, WA) |
Method and system for fast maximum a posteriori decoding
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular circuits, circuit components, techniques, etc. in order to provide a t... Read More
Inventors: Lerzer, Jurgen;, Assignee: Telefonaktiebolaget LM Ericsson (publ) (Stockholm, SE) |
Turbo decoder control for use with a programmable interleaver, variable block length, and multiple code rates
A control for a turbo decoder utilizing a MAP decoding algorithm comprises an address generator for addressing systematic data symbols, parity data symbols, and systematic likelihood ratios according ... Read More
Inventors: Van Stralen, Nick Andrew; Hladik, Stephen Michael; Itani, Abdallah Mahmoud; Wodnicki, Robert Gideon; Ross, John Anderson Fergus;, Assignee: General Electric Company (Niskayuna, NY) |
Method and apparatus for turbo decoding of trellis coded modulated signal transmissions
Briefly, the present invention implements an iterative decoding system within a Trellis Coded Modulation communications environment. The improved Trellis-coded modulation transmitter and receiver syst... Read More
Inventors: Xin, Weizhuang; Kong, Ning;, Assignee: Skyworks Solutions, Inc. (Newport Beach, CA) |
Semiconductor integrated circuit boundary scan test with multiplexed node selection
The object of the present invention is therefore to provide a semiconductor integrated circuit having a test circuit built therein to facilitate the board test of massproduced printed circuit boards h... Read More
Inventors: Imai, Kiyoshi; Tsuji, Toshiaki; Takada, Taku; Taguchi, Seiichi;, Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP) |
Testing the integrity of an electrical connection to a device using an onboard controllable signal source
OF THE INVENTION The present invention is directed to systems and a method for testing the integrity of an electrical connection mounted on a circuit assembly using an onboard controllable signal sou... Read More
Inventors: Brooks, Leslie Mayes;, Assignee: ZEN Licensing Group LLP (Atlanta, GA) |
Apparatus for I/O leakage self-test in an integrated circuit
According to one embodiment, an integrated circuit is disclosed that includes a first input/output (I/O) circuit and a leakage detection circuit coupled to the first I/O circuit. The leakage detection... Read More
Inventors: Frodsham, R. Tim; O'Brien, David J.;, Assignee: Intel Corporation (Santa Clara, CA) |
Mechanism for enabling compliance with the IEEE standard 1149.1 for boundary-scan designs and tests
The present invention provides a mechanism for boundary-scan design and test methodologies applicable to timing-critical high (above 200 MHz) speed clock designs, which complies with the IEEE standard... Read More
Inventors: Chung, Sung Soo;, Assignee: Cisco Technology, Inc. (San Jose, CA) |
Independent remote computer maintenance device
It is an object of the present invention to provide an independent computing device for diagnosing and repairing a host computer. It is another object of the present invention to provide an independen... Read More
Inventors: Worley, Christian B.; Worley, Allan L.;, Assignee: Worley; A. (Grand Junction, CO); Worley; C. (Salt Lake City, UT) |
Method, system, and program for diagnosing a computer in a network system
OF THE PREFERRED EMBODIMENTS In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several embodiments of the present invention. I... Read More
Inventors: Merriam, Greg Elliot;, Assignee: International Business Machines Corporation (Armonk, NY) |
System and method for identifying executable diagnostic routines using machine information and diagnostic information in a computer system
FIG. 1 is a diagram illustrating an embodiment of a computer system. FIG. 1 depicts a computer system 100. Computer system 100 includes a processor 110, a chipset 120, a memory 130, and a plurality o... Read More
Inventors: Brundridge, Michael A.; Jimenez, Javier L.;, Assignee: Dell Products L.P. (Round Rock, TX) |
Methods for quantitative analysis by tandem mass spectrometry
Embodiments of the present invention provide methods for deconvoluting contributions of a plurality of analytes utilizing a tandem mass spectrometry, or MS.sup.n signal. A tandem mass spectrometry sig... Read More
Inventors: Kushnir, Mark M.; Rockwood, Alan L.; Nelson, Gordon J.;, Assignee: University of Utah (Salt Lake City, UT) |
Design-for-testability method for path delay faults and test pattern generation method for path delay faults
OF THE INVENTION First Embodiment A first embodiment of the present invention relates to a design-for-testability method of changing the design of an integrated circuit to facilitate a test on path d... Read More
Inventors: Hosokawa, Toshinori;, Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP) |
Method for optimizing test development for digital circuits
The present invention provides test patterns to detect timing related failures in large digital ICs, to rapidly detect least slack paths. Such digital ICs typically include a plurality of gates, such ... Read More
Inventors: Fetherson, R. Scott;, Assignee: Fetherston; R. Scott (Pleasanton, CA) |
Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
OF THE INVENTION The present invention provides a switchable pull-up circuit particularly well-suited for use in IDDQ testing of integrated circuits having input and output signal lines with pull-ups... Read More
Inventors: Colwell, Michael; Rajsuman, Rochit; Abrishami, Ray; Sarkari, Zarir B.;, Assignee: LSI Logic Corporation (Milpitas, CA) |
Testing of digital-to-analog converters
In general, a technique for testing digital-to-analog converters includes providing a set of digital input signals to the digital-to-analog converters and comparing a resulting combined output signal ... Read More
Inventors: Kakizawa, Akira; Ortega, Carlos A.; Arellano, Mark A.;, Assignee: Intel Corporation (Santa Clara, CA) |
Method and apparatus for failure detection utilizing functional test vectors and scan mode
OF THE INVENTION A method and software for failure detection of logic nodes within an integrated device utilizing functional test vectors and scan mode are described. In the following description, fo... Read More
Inventors: Kakizawa, Akira; Fought, Erik T.;, Assignee: Intel Corporation (Santa Clara, CA) |
Testing apparatus embedded in scribe line and a method thereof
The object of the present invention therefore is to provide a testing apparatus embedded in a scribe line and a testing method thereof, which can increase the testing speed and decrease the testing co... Read More
Inventors: Bu, Lin-Kai; Hung, Kun-Cheng;, Assignee: Himax Technologies, Inc. (Tainan, TW) |
Method and apparatus for light-controlled circuit characterization
Principles of the present invention provide light-controlled circuit characterization techniques. For example, in one aspect of the invention, a technique for testing an integrated circuit includes th... Read More
Inventors: Song, Peilin; Stellari, Franco;, Assignee: International Business Machines Corporation (Armonk, NY) |
Method and system for instrumenting simulation models
It is therefore an object of the invention to provide a method and system for interactively designing and simulating complex circuits and systems, particularly digital devices, modules and systems. It... Read More
Inventors: Bargh, John Fowler; Hunt, Bryan Ronald; Roesner, Wolfgang; Williams, Derek Edward;, Assignee: International Business Machines Corporation (Armonk, NY) |
Facilitating simulation of a model within a distributed environment
The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a method of facilitating processing of models in a distributed environment. The method in... Read More
Inventors: Rich, Marvin J.; Mellors, William K.;, Assignee: International Business Machines Corporation (Armonk, NY) |
Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions
The aforementioned and other features are accomplished, according to the present invention, by providing an instruction, hereinafter referred to as the DRAIN instruction, and apparatus supporting that... Read More
Inventors: Cutler, David N.; Orbits, David A.; Bhandarkar, Dileep; Cardoza, Wayne; Witek, Richard T.;, Assignee: Digital Equipment Corporation (Maynard, MA) |
Fault Detection 
