 Asynchronous transfer mode based service consolidation switch |
| From the foregoing, a need has arisen for a telecommunications switch that integrates a variety of ... |
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| High-speed data bus for network switching |
| The specification will be organized as follows: 1. BlazePath.TM./BlazeFire.TM. Architecture/Chip S... |
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| Method and apparatus for data buffer management in a communications switch |
| OF A PREFERRED EMBODIMENT OF THE INVENTION Generally, the present invention provides a method and ... |
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| Handling contiguous memory references in a multi-queue system |
| What is claimed is: 1. A controller for a random access memory comprises: control logic, including ... |
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| Communication between processors |
| Referring to FIG. 1, a computer system 26 includes two processors 1, 2. Each processor 1, 2 has a ... |
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| Optimizations to receive packet status from fifo bus |
| According to one aspect of the invention, a method is described of receiving bytes of data from a ... |
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| Storing frame modification information in a bank in memory |
| The present invention comprises a method and system for reserving frame modification information ... |
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Apparatus and method for handling multiple mergeable misses in a non-blocking cache
| Details |
Inventors: Mehrotra, Sharad; Hetherington, Ricky C.; Wong, Michelle L.;
Assignee: Sun Microsystems, Inc. (Palo Alto, CA)
Primary Examiner: Cabeca; John W.
Assistant Examiner: Tran; Denise
Attorney, Agent or Firm: Langley; Stuart T., Kubida; William J. Hogan & HartsonLLP
A method and apparatus for merging multiple misses to a multi-level cache is provided to improve the performance of the cache. A first and second non-blocking cache are each provided with miss queues storing entries corresponding to access requests not serviced by the respective caches. The first and second miss queues have an indicator associable with each of said entries in the respective miss queues indicating that the entry is a primary reference to data located at the address associated with said entry. If a subsequent instruction generates a cache miss accessing data associated with an entry in a miss queue, the subsequent miss is merged with the appropriate entry in the miss queue and serviced when the primary reference is serviced. |
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DETAILED DESCRIPTION In light of the above, therefore, according to a broad aspect of the invention, disclosed herein is a multi-level cache and method for merging cache misses which access the same line of a non-blocking cache.
Merging of cache misses improves the performance of the cache memory system, as well as the processor, by servicing misses to the cache which access the same line of the cache as a primary miss to the cache.
The method includes the steps of detecting if a first instruction generates a first cache miss, and marking the first cache miss as a primary reference.
A servicing step services the first cache miss with a line of data.
A detecting step detects if the second instruction generates a second cache miss which accesses the data provided by the servicing step.
The second cache miss is serviced with at least a portion of the data provided by the servicing step.
In this manner, the secondary references do not independently generate requests into the higher level caches which create additional cache activity and slow the cache memory's performance.
A signaling step can be included to signal the processor that the second cache miss was serviced.
The detecting step can include comparing a memory address accessed by the second instruction against a memory address accessed by the first instruction.
A buffer, such as a miss queue, can be provided to the first and second non-blocking caches for storing instructions which access memory associated with the first and second miss respectively, along with an indicator associable with each instruction in the buffers indicating that the associated instruction is a primary reference to data located at the address specified by the instruction.
An appending step can append an instruction identifier of a secondary reference to an instruction stored in the buffer if the instruction accesses data to be provided by the servicing step.
According to another broad aspect of the invention, a cache memory is disclosed which can merge cache misses to the same line of the cache
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