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 Bios storage array

Details
Inventors: Nalawadi, Rajeev K.; Thai, Dong;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Sparks; Donald
Assistant Examiner: Diller; Jesse
Attorney, Agent or Firm: Huter; Jeffrey B.

Methods, apparatus and machine readable medium are described in which BIOS initialization code divides one or more storage devices into two or more portions. Further, a BIOS device handler may use the portions of the divided storage devices to implement a storage array that provides attributes of one or more RAID levels.

DETAILED DESCRIPTION In the following detailed description, numerous specific details are described in order to provide a thorough understanding of the invention.
However, the present invention may be practiced without these specific details.
In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, example sizes/models/values/ranges may be given, although some embodiments may not be limited to these specific examples.
References in the specification to "one embodiment", "an embodiment", "an example embodiment", etc.
, indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic.
Moreover, such phrases are not necessarily referring to the same embodiment.
Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Further, the terms "first", "second", "third", etc.
are used herein as labels to distinguish between similarly named components and/or operations.
In particular, such terms are not used to signify and are not meant to signify an ordering of components and/or operations.
Further, such terms are not used to signify and are not meant to signify one component and/or operation having greater importance than another.
An example embodiment of a computing device 100 is shown in FIG.
1.
The computing device 100 may comprise one or more processors 102.
sub.
1 .
.
.
102.
sub.
P that are coupled to a chipset 104 via a processor bus.
The chipset 104 generally interconnects the one or more processors 102.
sub.
1 .
.
.
102.
sub.
P with memory 106, firmware 108, a storage device (SD) controller 110, one or more storage devices 112



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