Bus arbitration and resource management for concurrent vector signal processor architecture

DETAILED DESCRIPTION These and other objects, features and advantages are achieved by the concurrent vector signal processor architecture disclosed herein.
To support concurrent operation of the concurrent vector signal processor an original mechanism of resource allocation and bus arbitration has been introduced.
The concurrent vector signal processor architecture allows concurrent execution of different types of instructions if (and only if) they share no internal resources.
Internal resources can be divided into two distinct groups.
An availability of resources from both groups is checked by the Resource Manager before new instruction initialization.
The instruction sequence is split in a number of subtasks that require different processing units to be executed.
Internal and external buses operation is controlled by the Arbiter, which allocates the buses to one of the processing units in accordance with requests and priority scheme.
The bus allocation is valid for a single instruction cycle and the whole process is renewed every cycle.