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Details
Inventors: Leddige, Michael W.; McCall, James A.;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Elmore; Stephen C.
Assistant Examiner:
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman LLP

Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA signal is routed to a first of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal is then divided into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM. The CA signal components are then recombined and routed to the second DIMM. The recombined CA signal is then divided again into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM and the CA signal components are then recombined. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM.

DETAILED DESCRIPTION Embodiments of the invention provide a memory CA bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation.
For one embodiment of the invention the CA signal is routed to a centrally located DRAM on a first DIMM of a multi-DIMM/channel memory bus design.
At this point the CA signal is divided and a CA signal component is routed to a group of DRAMs on one portion of the DIMM while other CA signal components are routed to other groups of DRAMS on the first DIMM.
The CA signal components are then routed sequentially through each DRAM of a group of DRAMs on the respective portions of the first DIMM.
The CA signal components are then recombined and transmitted to a second DIMM.
The process is continued until the CA signal has been routed to all DIMMs of the multi DIMM memory bus design.
In one embodiment, after routing through the last DIMM, the CA signal is terminated at a termination point on the last DIMM.
In an alternative embodiment, the CA signal is terminated on the motherboard after routing through the last group of DRAMs and recombining on the last DIMM.
In the following description, numerous specific details are set forth.
However, it is understood that embodiments of the invention may be practiced without these specific details.
In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.
Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention.
Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment.
Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments



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