Communication between processors

DETAILED DESCRIPTION Referring to FIG.
1, a computer system 26 includes two processors 1, 2.
Each processor 1, 2 has a corresponding static random access memory (SRAM) 21, 22 for storing data that needs to be accessed with a low latency and a corresponding synchronous dynamic random access memory (SDRAM) 23, 24 for processing large volumes of data.
The processors 1,2 each have an Fbus FIFO 3, 4, which is connected to a 64-bit FIFO bus 25, for communicating to peripheral devices, such as media access controller (MAC) 16.
MAC 16 may be a Gigabit Ethernet device that complies with the IEEE 802.
3z standard.
MAC 16 has two data ports 17, 18.
Multiple peripheral devices may be concurrently connected to the FIFO bus 25.
Through the FIFO bus 25, each of the processors 1, 2 can communicate with any peripherals 16 connected to the FIFO bus.
At any time, one processor ("the master") controls the FIFO bus 25 using signals sent over the Ready Control Bus 14, while the other processor ("the slave") responds to instructions from the master.
In FIG.
1, processor 1 is the master while processor 2 is the slave.
The master controls communications on the first-in-first-out-buffer (FIFO) bus using signals sent on a 5-bit Ready Control Bus 14.
The signals allow the master to directly address a device or a slave processor on the bus and to send a query to determine whether the device is ready to transmit (TRRdy) or receive (RRdy) data on the bus.
The computer system may include a decoder 15 for decoding signals from the Ready Control Bus into a single TRRdy signal 19 and a single Rrdy signal 20 for a device 16 on the bus.
Additionally, the computer system includes an 8-bit Ready Bus 13, which is used by the master processor 1 to control data flow on the devices on the FIFO bus 25.
For example, master processor 1 may use the Ready Bus 13 to direct MAC 16 to send data from port 1 instead of sending data from port 2 onto the bus.
Each processor 1, 2 has a send FIFO 9, 10 for buffering data elements that are to be sent on the Ready Bus 13, and a get FIFO 11, 12 for buffering data elements that are received from the Ready Bus 13