Computer node architecture comprising a dedicated middleware processor

DETAILED DESCRIPTION OF THE INVENTION FIG.
1 shows a system of four multicomputer node computers that exchange data via a common bus 101.
Each node computer is provided with a communication controller 100 to the common bus 101, a process I-O controller 110 connected to the sensors and actuators 111, as well as a middleware computer 120 with a CPU of its own and a host computer 140.
FIG.
2 furthermore shows the inner structure of a multicomputer node computer.
The communication controller 200 is connected to the common bus 101 by way of a stub line 201.
Via lines 211 or via a field bus the I-O controller 210 reads and writes the signals to the sensors and actuators 111.
The two controllers, the communication controller 200 and the I-O controller 210 are both controlled by the middleware computer 220.
The middleware computer 220 is provided with a memory and a CPU of its own as well as with the software needed.
A data interface 230 between the middleware computer 220 and the host computer 240 is formed by a common memory range ("dual ported RAM") which may be addressed by the two computers.
In a data structure 225 there is indicated when the middleware computer 220 is allowed to write into the data interface 230 to the host computer 240 and when it is allowed to read from said interface 230.
In an analogous manner, there is indicated in a data structure 235 when the host computer 240 is allowed to write into the data interface 230 and when it is allowed to read from said interface.
When all the communication controllers 100 which are connected via the bus 101 build up a global time together, said global time is periodically written into a register 202 and concurrently, per hardware via a signal line 221, into a register 231 in the interface 230 between the middleware computer 220 and the host computer 240.
A method for building up a global time in a distributed computer system has been published in the European Patent EP 658 257 and in the U.
S.
Pat.
Nos.
4,866,606 and 5,694,542.
Finally, the interface 230 between middleware computer 220 and host computer 240 may also include a timer that generates a hardware-interrupt in the host computer 240 when the content of the time cell 231 reaches a value recorded in the distinct memory cell 232 in the interface 230 by the host computer 240 for example