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Content-addressable memory
| Details |
Inventors: Hanawa, Makoto; Nakazawa, Takuichiro;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Popek; Joseph A.
Assistant Examiner:
Attorney, Agent or Firm: Fay, Sharpe, Beall, Fagan, Minnich & McKee
A content-addressable memory which has a storage bit cell (121, 122), signal supplying circuits (380, 390, 400) and comparison circuits (125, 126, 127, 128). The storage bit cell (121, 122) holds a first data (D) and a second data (D) of opposite phases. The signal supplying circuits (380, 390, 400) supply a first signal (a1) and a second signal (a1), respectively, to a first data line (180) and a second data line (190) of the storage bit cell (121, 122) in response to an input signal (A1) and a control signal (510). The first and second signals (a1, a1) are in opposite phases. The comparison circuits (125, 126, 127, 128) detect the relation between the first (D) stored in the storage bit cell (121, 122) and the first signal (a1) on the first data line (180) supplied from the signal supplying circuits (380, 390, 400) and the relation between the second data (D) stored in the storage bit cell (121, 122) and the second signal (a1) on the second data line (190) supplied from the signal supplying circuits (380, 390, 400). Wherein as part of the signal supplying circuit (380, 390, 400) circuit (400) dissolves the opposite phase relation between the first signal (a1) on the first data line (180) and the second signal (a1) on the second data line (190) in response to a control signal (510) and the input signal (A1). However, this circuit (400) does not dissolve the opposite phase relation when the input signal (A1) is "1" level and the control signal (510) is "1" level. |
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DETAILED DESCRIPTION The examination by this inventors, however, has found that the conventional content-addressable memory of known structure has the following drawbacks.
That is, the OR circuit in the content-addressable memory is needed only for fault detection and not necessary for normal operation of the memory.
Thus, the OR circuit increases the number of circuit elements of the content-addressable memory as well as the cell size, which in turn leads to an increased size of hardware of the content-addressable memory as a whole.
Furthermore, the OR circuit, since it is connected in series with the output of the comparison means, causes a delay in the data reading from the content-addressable memory.
Based on the result of the above examination, this invention is accomplished to permit high-speed reading of the contents of the content-addressable memory cells and facilitate the fault check on the content-addressable memory by minimizing an increase in added hardware.
The outline of this invention disclosed in the following description may be summarized as follows.
The content-addressable memory according to this invention comprises: (1) storage bit cells 121, 122 holding first data (D) and second data (D), the two data in opposite phases; (2) signal supplying means 380, 390, 400 for supplying first signal al and second signal al, the two signals in opposite phases, to first data line 180 and second data line 190 respectively in response to an input signal Al; and (3) comparison means 125, 126, 127, 128 for detecting the relation between the first data D and the first signal al and between the second data Dand the second signal al; wherein the signal supply means 380,390, 400 have a means 400 to dissolve the opposite-phase relation between the first and second signals al, al in response to a control signal 510.
When the opposite-phase relation is dissolved, the first and second signals al, al are virtually equal in level.
Therefore, comparison by the comparison means 125, 126, 127, 128 becomes impossible, allowing the storage bit cell 121, 122 to be masked
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