Distributed processing memory chip with embedded logic having both data memory and broadcast memory

DETAILED DESCRIPTION The present invention provides computer memory chips which include internal computational logic and secondary memory that may be broadcast to in all chips simultaneously and systems with such memories.
The memory chips may have a standard package pin configuration.
The architecture allows easy expansion of the number of parallel Processing Elements by simply increasing the number of chips and permits massively parallel processing.
The chips may also operate as conventional RAMs.
(Random Access Memories).
This solves known system problems by minimizing the need for board level data movement.
The chips achieve this by combining storage with computation and reducing the amount of data sent to the main CPU.
A first order estimate of system throughput increase is given by the ratio of raw data to "information" data.
For example, in the case of matrix multiplication (to be described in detail later), assume that two bytes of information is the result obtained from 256 raw bytes.
Thus, the system improvement is evident in that only two bytes of information are brought to the CPU rather than 256 raw numbers.
That is, an improvement by a factor of 128.
Depending on the amount of data path logic included in the chips and the number of chips included in the system, the number of MIPS and the throughput improvement may be orders of magnitude higher than the 128 of the previous example.
The design of the chip allows easy expansion to provide the desired amount of distributed parallel processing power by simply increasing the number of chips.
The economics of the commodity memory business force participants to maximize device density while minimizing process and package costs.
The transfer of computational workload from the CPUs to the memories takes advantage of memory manufacturing discipline while greatly reducing the required CPU bus bandwidth.
The preferred embodiment design also allows the system designer flexibility in setting processing power vs cost as the number of processing elements is defined by the memory chip count