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Details
Inventors: Wolrich, Gilbert; Rosenbluth, Mark B.; Bernstein, Debra;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Padmanabhan; Mano
Assistant Examiner: Namazi; Mehdi
Attorney, Agent or Firm: Fish & Richardson P.C.

The use of enqueue operations to append multi-buffer packets to the end of a queue includes receiving a request to place a string of linked buffers in a queue, specifying a first buffer in the string and a queue descriptor associated with the first buffer in the string, updating the buffer descriptor that points to the last buffer in the queue to point to the first buffer in the string, and updating a tail pointer to point to the last buffer in the string.

DETAILED DESCRIPTION Referring to FIG.
1, a network system 10 for processing data packets includes a source 12 of data packets coupled to an input of a network device 14.
An output of the network device 14 is coupled to a destination 16 of data packets.
The network device 14 can include a network processor 18 having a memory for operating on memory data structures.
The processor executes instructions and operates with the memory data structures as configured to store and forward the data packets to a specified destination.
Network device 14 can include or be part of, for example, a network switch or a network router.
The source of data packets 12 can include other network devices connected over a communications path operating at high data packet transfer line speeds, such as, an optical carrier 10 gigabit line (i.
e.
, OC-192) or other line speeds.
The destination 16 of data packets can include a similar network connection.
Referring to FIG.
2, the network processor 18 has multiple programming engines that function, respectively, as a receive pipeline 21, a transmit scheduler 24, a queue manager 27 and a transmit pipeline 28.
Each programming engine has a multiple-entry content addressable memory (CAM) to track N of the most recently used queue descriptors where N is the number of entries in the CAM.
For example, the queue manager 27 includes the CAM 29.
The network processor 18 includes a memory controller 34 that is coupled to a first memory 30 and second memory 32.
A third memory 17 includes software instructions for causing the engines to operate as discussed in detail below.
Although the present implementation uses separate memories, a single memory may be used to perform the functions of the first and second memory mentioned above.
The memory controller 34 initiates queue commands in the order in which they are received and exchanges data with the queue manager 27.
The first memory 30 has a memory space for storing data.
The second memory 32 is coupled to the queue manager 27 and other components of the network processor 18



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